This page lists posters accepted for publication.

Quick link to reach posters presented each day:

• Tuesday 6th.
• Wednesday 7th
• Thursday 8th.

Posters are sorted by alphabetical order of presenter’s last name.

But first of all, a few remarks for the poster presenters:

• Preparation before the conference:
  • Posters shall be printed in A0 format, in portrait mode.
  • Each presenter shall bring his own poster on site.
  • There are no RISC-V Summit Europe template for posters.
  • The final version of the two pages extended abstract shall be povided according to the template provided in https://github.com/riscv-europe/riscv-europe-summit-templates.
• About poster sessions:
  • As far as possible, posters have been dispatched throughout the three days to match topics addressed in the plenary track of the day.
  • Each poster will be displayed for a full day.
  • Presenters are expected to stand next to their posters during breaks, lunches, and during the early evening cocktail on Tuesday 6th.
  • In order to allow authors to attend the conference pleanry track, the exhibition and poster area will be open only during breaks and lunches, plus on Tuesday 6th, during the on-site cocktail in late afternoon.
• Administrativia:
  • At least one author of the poster must register for the core conference (Tue-Thu). Posters without registered authors will not be put on display nor referenced on the web site.
• Publication on the conference web site:
  • The final version of the extended abstract shall be provided as PDF before the conference for publication on the web site.
  • A < 150 words summary, a < 150 words bio of the presenter, together with his affiliation and URLs shall be provided by mail to be used in the program on the conference web site.
  • The final version of the posters may also be provided for publication. This is not mandatory but highly recommended.
  • The final PDF version of the abstract, the 150 words bio and summary, and the poster PDF, if applicable, shall be sent to europe-slides-posters-final@riscv.org.

Posters on Display Tuesday June 6th

Presenters are expected to be with their poster during the morning break, lunch and afternoon break, as well as during the early evening cocktail on Tuesday 6.

Jingzhou Li – Falcon: A Dual-Core Lockstep Microprocessor Based on RISC-V ISA

Jingzhou Li (Tsinghua University, Beijing, China) , Huaiyu Chen, Wenbin Zhang, Hu He.

Poster #1 in MR07-08 on Tue 6th. Links: extended abstract, poster.

Summary

Functional safety is a crucial consideration in the development of road vehicles. Microcontrollers (MCUs) that operate in high-safety automotive systems typically incorporate lockstep mechanisms to detect errors and enhance safety. In this study, we introduce Falcon, a dual-core lockstep automotive MCU that utilizes the RISC-V ISA. Falcon employs a lightweight, off-core-level Sphere of Replication (SoR) that necessitates minimal modifications to the original microarchitecture. It assesses certain critical signals of the primary and checker cores to identify possible soft errors while avoiding potential spatial-temporal coupling failures. The main core supports RV32IMAFDC with 6 execution units and is compatible with AHB/AXI interfaces. Falcon also incorporates an interrupt controller. This study demonstrates that RISC-V ISA-based MCUs can have a wide-ranging application space in the high-safety automotive processor field.

Bio

Jingzhou Li is a PhD student from the School of Integrated Circuits, Tsinghua University. He received his Bachelor of Science degree from the Department of Physics, Tsinghua University in 2020. Jingzhou Li’s research interests are in Computer Architecture and Integrated Circuit design, with a focus on CPUs and GPUs. Jingzhou Li is a member of Professor Hu He’s group and has participated in several programs such as Egret (a 32bits RISC-V processor), Falcon(a dual-core lockstep processor), and Ventus(an open source RISC-V GPGPU).

Mehdi Akeddar – An opensource framework for edge-to-cloud inference on resource-constrained RISC-V systems

Mehdi Akeddar , Thomas Rieder, Guillaume Chacun, Bruno Da Rocha Carvalho, Marina Zapater.

Poster #2 in MR07-08 on Tue 6th. Links: extended abstract, poster.

Summary

In recent years we are witnessing an increasing adoption of RISC-V based systems to run Artificial Intelligence (AI) inference tasks. This trend spans to visual navigation, where major players start adopting RISC-V for autonomous driving. Still, RISC-V based edge devices fall short in providing the performance requirements of complex AI inference. Our work tackles the previous challenges by proposing an opensource framework for transparent distribution of visual navigation inference tasks between edge and cloud for resource-constrained RISC-V edge devices. Our framework automates the partitioning of ONNX and TFLite models between a RISC-V accelerated nanodrone equipped a GAP8 system-on-chip and a cloud server. Our results showcase how partial inference improves the performance achieve by drone-only inference.

Bio

Mehdi Akeddar is a machine learning engineer at REDS Lab at HEIG-VD. He received a Master’s degree in Medical Robotics from EPFL in 2022, where he developed his expertise in robotics, computer science, and rehabilitation technologies. Mr. Akeddar’s current work focuses on developing machine-learning algorithms for embedded systems.

Shahzaib Muhammad Kashif – ChipShop: A Cloud-Based GUI for Accelerating SoC Design

Shahzaib Muhammad Kashif (Usman Institute Of Technology (uit), Karachi, Pakistan) , Talha Ahmed, Farhan Ahmed Karim, Mahnoor Ismail.

Poster #3 in MR07-08 on Tue 6th. Link: extended abstract.

Summary

ChipShop is a cloud-based graphical user interface (GUI) that democratizes system-on-chip (SoC) design by simplifying the configuration and acceleration process on the open-source Chipyard platform. This user-friendly platform enables users to easily configure core types, caches, memory controllers, and other SoC features while supporting FPGA emulation, mapping, and the addition of new intellectual properties (IPs). ChipShop of ers automatic blackbox generation and integration for user-provided RTLs, streamlining the design process and reducing errors. The platform also includes real-time collaboration and version control features, making it ideal for large teams working on complex designs. Future plans for ChipShop involve expanding its functionality to support FireSim and Bitstream Generation through free and open-source tools like F4PGA.

Bio

Shahzaib Kashif is a Research Assistant of Micro Electronics Research Lab (MERL) Pakistan. He is one of the Pioneers who introduced the Semiconductor Revolution in the form of Open-Source RISC-V ISA in Pakistan in the year 2019.

Siqi Zhao – Hardware-Assisted Virtual IOMMU with Nested Translation

Siqi Zhao (T-head Semiconductor, Hangzhou, China)

Poster #4 in MR07-08 on Tue 6th. Links: extended abstract, poster.

Summary

Passthrough devices is the default option for high-performance I/O for virtual machines. However, a virtual machine cannot efficiently nor transparently take advantage of a virtual IOMMU to manage device assigned to it, due to the fact that existing solutions for virtual IOMMU is based on emulation or paravirtualization. This extended abstract describes a hardware-assisted design for providing efficient and transparent virtual IOMMU for virtual machines.

Bio

Dr. Siqi Zhao works in the architecture group of T-Head Semiconductor. He is an active member in the RISC-V community and serves as the chair of the Unified Discovery Task Group.

Bob Frankel – Introducing Em – Taking RISC-V Software Over The Edge

Bob Frankel (Bespoke IoT, Santa Barbara, United States)

Poster #5 in MR07-08 on Tue 6th. Links: extended abstract, poster.

Summary

The Em programming language elevates embedded firmware development to a higher-level which has historically eluded C. Originally conceived in the 2009-2010 timeframe, Em has evolved over the last decade through a series of commercial deployments in low-power, low-cost wireless IoT applications. Thanks to novel optimization techniques employed by the underlying language translator, Em programs would invariably out-perform their hand-crafted C counterparts in terms of time and (especially) space. Initial engagement with RISC-V began last year through Em support for two development boards used for edge-processing. With tenfold reductions in program footprint not uncommon, opportunities abound to target small RISC-V MCUs and SoCs with less than 32K of memory – pushing conventional edge-processing designs to the IoT fringe in terms of silicon size and power consumption.

Bio

Bob Frankel has been involved in the design, development, and deployment of embedded system software for over 40 years. Acknowledged as the “father of DSP operating systems”, he co-founded Spectron Microsystems in 1987, whose SPOX and DSP-BIOS products became de-facto industry standards. Texas Instruments subsequently acquired Spectron in 1998, where Frankel (aka “BIOS BOB”) was elected TI Fellow and served as the company’s Chief Software Strategist. After retiring from TI, he co-founded Emmoco in 2011, whose BlueJoule IoT platform provided the impetus for an acquisition by Shelfbucks in 2015 – where Bob worked for several years as a strategic advisor, as a platform architect, and as an embedded programmer. Bob then co-founded Bespoke IoT in 2019, where he’s currently focused on delivering tailored solutions for low-power, long-range, low-cost wireless communication within high-volume IoT applications. Bob received an MS in Computer Science from the University of Pennsylvania, after pursuing undergraduate and graduate studies in the History and Theory of Music. He’s been playing the flute/piccolo since 4th grade, and has more recently taken up the double-bass.

Enrique S. Quintana-ortí – Parallelizing BLIS-style Matrix Multiplication for TinyML on Ultra-Low-Power multicore RISC-V

Enrique S. Quintana-ortí (Universitat Politècnica de València, Valencia, España) , Cristian Ramirez, Adrián Castelló.

Poster #6 in MR07-08 on Tue 6th. Link: extended abstract.

Summary

We present our BLIS-like general matrix multiplication ( gemm) for the multicore RISC-V processor embedded in the GAP8 platform, and evaluate the parallel performance of this computational kernel in a deep learning (DL) scenario. Concretely, we leverage the IM2COL approach to transform the convolution layers into gemm, and develop a parallelized algorithm tailored for this ultra-low-power processor, targeting DL inference with a MobileNet-v1 convolutional model. Our experimental results demonstrate that the gemm algorithm achieves a significant speed-up compared to the sequential version. This work thus contributes to the development of high-performance and energy-efficient machine-learning applications for multicore RISC-V processors.

Bio

Cristian Ramírez is a graduate of Telecommunications Engineering (mention in Electronics) from the Technical University of Loja, Ecuador, and holds a master’s degree in electronic systems Engineering and Computer Science from the Polytechnic University of Valencia, Spain. He is currently a Santiago Grisolia Fellow, supported by the Generalitat Valenciana, and part of the “Energy-Aware High-Performance Computing and Communications” project. As a Ph.D. student in the Parallel Architectures Group (GAP), he implements artificial intelligence models in heterogeneous architectures.

Balaji Chegu – Software Hardware Co-processing in RISC-V using OpenVX™ for Embedded Vision Applications

Balaji Chegu (Microchip, Bangalore, India) , Prakash Reddy Battu, Yogesh Agrawal, Arun Naik.

Poster #7 in MR07-08 on Tue 6th. Links: extended abstract, poster.

Summary

The complexity of computation logic in embedded vision applications is on the rise due to increase in video resolutions and image quality requirements. There are many frameworks that support acceleration of embedded vision applications, such as OpenVXTM [1]. It is a royalty-free cross platform framework using connected graph representation of operations In OpenVXTM, image operations are expressed as graph of nodes, where nodes can be run on hardware or software. Typically, the run functions of the computationally complex nodes can be optimized in specialized hardware logic like FPGA to achieve acceleration and thus better FPS (frame per second). The graph is represented in C/C++ and is hosted on OS like Linux. This paper explains the acceleration of 2D convolution as OpenVXTM run functions using a Generic Matrix Multiplier (GMM) implemented in FPGA logic and summarizes the benefits of the proposed architecture by comparing the execution times and frame rates with and without FPGA acceleration.

Bio

Balaji Chegu was born on August 29th, 1983 in India. He received his Bachelor of Technology (B.Tech), in Electronics and Communications of Engineering from SVUCE. He completed his Masters of Technology with a specialization is Digital Signal Processing from Indian Institute of Technology, Guwahati (IITG) in 2007. For the past 15 years he has been actively working in technical roles of DSP, Digital Image and Video processing. His research interests include heterogeneous computing, edge computing and neural networks.

Jaime Palacios – Towards a RISC-V Educational HW Lab

Jaime Palacios (Universidad de Cantabria, Cantabria, Spain) , Vladimir Mateev, Borja Pérez, Cristóbal Camarero, Pablo Fuentes, Carmen Martínez.

Poster #8 in MR07-08 on Tue 6th. Links: extended abstract, poster.

Summary

Hardware-centric courses at Computer Science and Engineering degrees benet from using a HW-based approach following an actual computer ISA and an autonomous lab setup for practical sessions. Prior teaching experiences using proprietary ISAs have shown the success of our methodology. However, the RISC-V architecture is an appealing alternative due to its open nature and potential for pervasiveness. This work explores the path towards using RISC-V architecture in the courses and the HW and SW needs that need to be adresssed.

Bio

Jaime Palacios is a MSc student in computer science at Universidad de Cantabria. Jaime received his BSc from Universidad de Cantabria in 2022, with a final project on the development of a remote HW lab setup based on Raspberry Pi boards for teaching purposes. Jaime is currently affiliated to the Departamento de Ingeniería Informática y Electrónica, Universidad de Cantabria. His research focuses on the analysis and performance evaluation of high-performance interconnection networks

Javier Mora – A three perspective analysis of RISC-V design tools for safety and security architectures

Javier Mora (Collins Aerospace, Cork, Ireland) , Alejandro García-Gener, Gonzalo Salinas Hernando.

Poster #9 in MR07-08 on Tue 6th. Links: extended abstract, poster.

Summary

Aerospace industry requirements for SoC design demand high reliability and fault tolerance techniques while maintaining high standard performance in harsh environments and autonomous complex applications. The emergence of RISC-V architectures and toolsets offers a new paradigm for ASIC design, promising to accelerate and facilitate the design, verification, and testing of ASICs, reducing design time and costs. This work aims to demonstrate the feasibility of designing safe and secure architectures under the umbrella of open-source tools based on RISC-V. The safety and security constraints are analysed from three perspectives: hardware solutions and architecture definition at design level, the introduction of external IPs in the design with redundant techniques, and fault detection and mitigation techniques from external factors. The results indicate that RISC-V-based tools can be utilized to develop reliable and secure aerospace systems.

Bio

Javier Mora is a Principal Research Engineer in the Connected & Real-time Systems group at Collins Aerospace Ireland, a position he has held since June 2022, and had previously worked as a Staff Research Scientist in United Technologies / Raytheon Technologies in the same group for 2 years (2018-2020). Javier’s technical background is digital design and embedded systems design, with a strong focus on FPGA development and heterogeneous computation, and has extensive experience as a researcher. Javier has a Ph.D. in Electronic Engineering, which he obtained in 2019 from the Technical University of Madrid. The topic of his thesis was Evolvable Hardware based on Dynamic Partial Reconfiguration of FPGAs.

Marcello Barbirotta – Adding Dynamic Triple Modular Redundancy on a RISC-V Microarchitecture

Marcello Barbirotta (Sapienza University Of Rome, Roma, Italia) , Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri.

Poster #10 in MR07-08 on Tue 6th. Links: extended abstract, poster.

Summary

Fault Tolerance represents an important area for digital applications, so it has received recent acceleration in its development and evolution. Being able to understand how to protect electronic circuits, and in particular microprocessors, from the different types of SEE (Single Event Error) faults, frequent and internally divisible into other categories, is a very complex process [1], which sees the study and consequent implementation of these techniques for the hardware/software protection of the architectures under examination, making them more expensive and less performing than the respective non-redundant architectures. Safety and Reliability are, therefore, two key concepts in the technological world, and RISC-V plays an interesting role in this context for its inherent extendability and the availability of open-source microarchitecture designs.

Tobias Jauch – Detecting and Patching Transient Execution Side Channels in an Out-of-Order RISC-V Core

Tobias Jauch (RPTU Kaiserslautern-Landau, Kaiserslautern, Germany) , Alex Wezel, Mohammad Fadiheh, Dominik Stoffel, Wolfgang Kunz.

Poster #11 in MR05-06 on Tue 6th. Links: extended abstract, poster.

Summary

Transient Execution Side Channels in modern hardware systems are particularly hard to detect and even harder to mitigate efficiently. Our case study on the open-source out-of-order processor SonicBOOM highlights some of the difficulties and pitfalls involved. We detected that a vulnerability to Meltdown has been re-introduced to the design by minor hardware updates and that closing this gap can easily leave certain channels open or even introduce new ones, e.g., channels that are based on speculative interference. Furthermore, we show how these channels can securely be mitigated with the help of a formal verification tool.

Bio

Tobias Jauch received the M.Sc. degree in electrical and computer engineering in 2021 from Technische Universität Kaiserslautern, Kaiserslautern, Germany, where he is currently working toward the Doctoral degree with Electronic Design Automation Group of Prof. Wolfgang Kunz. His current research interests include hardware security, transient execution side channels, and methodologies for fixing vulnerable hardware designs.

Raúl de la Cruz – Providing QoS policies for mixed-criticality applications on RISC-V based MPSoCs

Raúl de la Cruz (Collins Aerospace, Cork, Ireland) , Gonzalo Salinas, Alejandro Garcia.

Poster #12 in MR05-06 on Tue 6th. Links: extended abstract, poster.

Summary

More integrated systems come at the price of harder predictability and determinism. This is specially true on MPSoCs with myriad shared resources that can behave as interference channels thus creating contention and nondeterministic behaviour. Variability makes MPSoCs very hard and expensive to certify for safety-critical systems. In order to ease the certification process and guarantee tasks’ timeliness, drastic measures are traditionally enforced in the system configuration. Some of these include the deactivation of resources to avoid contention scenarios, synchronization of core’s partitions using ARINC-653 schedulers and long provisioning of budget times increasing deadlines. These mitigation strategies impact drastically on the performance of the system, either underutilizing most of the advanced MPSoCs capabilities or reducing the integration level of mixed-criticality applications. This work proposes novel QoS strategies to enforce determinism of mixed-criticality applications while performance is preserved. The infrastructure has been successfully evaluated on a customized quad-core RISC-V RocketChip architecture using high assurance level applications with stringent deadlines.

Bio

Raúl de la Cruz is a Sr. Principal Research Engineer in the Connected & Real-Time Systems (CRS) group at Collins ART-Ireland with strong interests on high performance computing, performance analysis and computer architecture topics. He was a permanent PostDoc researcher in the CASE department at the Barcelona Supercomputing Center (BSC), the national supercomputing center in Spain, before joining Collins Aerospace in 2020. He has collaborated in different European H2020 funded projects such as MASTECS, LEGaTO, GrowSmarter and PRACE; and has also participated in joint collaboration projects with private companies such as Mitiga Solutions, IBM and Repsol. Currently, he is actively working on projects that will ease the adoption of MPSoCs and heterogeneous computing platforms in the aerospace domain providing safety measures for mixed-critical applications. He holds a BSc in Computer Science and a PhD on Computer Architecture from Polytechnic University of Catalonia, Spain.

Stefano Mercogliano – Enabling Virtualization on RISC-V Microcontrollers

Stefano Mercogliano (Unina, Napoli, Italy) , Daniele Ottaviano, Alessandro Cilardo.

Poster #13 in MR05-06 on Tue 6th. Links: extended abstract, poster.

Summary

This paper briefly provides the main motivations and goals to enable isolation and virtualization on MMU-less devices, introducing a high-level description of an extension meant to support virtualization on RISC-V microcontrollers through a set of new hardware mechanisms, concluding with an outline of our future directions.

Bio

I am a PhD student from the Department of Electrical Engineering and Information Technologies, University of Naples Federico II with a strong passion in computer architectures, low level programming, trekking and boardgames. My research interests revolve around microcontrollers security & safety along with bioinformatics genome-based workloads in the HPC domain. Since the beginning of my PhD I joined the world of open-source architectures with the RISC-V initiative to add my contribution to the low-level devices of the future.

Anthony Zgheib – Enhancing the RISC-V Trace Encoder to verify the control-flow and code execution integrity

Anthony Zgheib (CEA Leti, Aix-en-provence, France) , Pierre-alain Moellic, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max DUTERTRE.

Poster #14 in MR05-06 on Tue 6th. Links: extended abstract, poster.

Summary

This paper presents control-flow and code execution integrity solutions for programs running on RISC-V cores. Our solutions are based on the RISC-V Trace Encoder (TE) that provides information about the execution path of the user’s program. A first approach is compliant with the RISC-V TE standard. It detects instruction skip attacks on function calls and their returns and, attacks on branch instructions. A second approach implies an evolution of the TE specifications that permits to detect more complex fault models as the corruption of any discontinuity instruction. It covers more security properties as the program execution integrity. Our TE-based solutions were implemented on an IBEX RISC-V core and have efficiently detected simulated and experimental Fault Injection Attacks (FIA). Our verification systems do not modify the RISC-V Instruction Set Architecture (ISA), the compilation process or the user code.

Bio

I received an engineering master degree in microelectronics and computer science from Mines Saint-Etienne (EMSE) school, France, in 2019. I am a Ph. D. candidate at EMSE in the Secured Architectures and Systems (SAS) research department, which is part of a joint R&D team with the CEA Leti. My research interests are in the areas of control-flow and programs execution verification, fault injection attacks and RISC-V cores

Darek Palubiak – Evaluation of critical flip-flops in RISC-V cores using fault injection for improved single-event-upset resilience

Darek Palubiak (Cadence Design Systems, Cork, Ireland) , Vitali Karasenko, Connie O’Shea.

Poster #15 in MR05-06 on Tue 6th. Link: extended abstract.

Summary

In this paper, we present the application of fault injection simulations to identify and selectively harden the most ciritical flip-flops of RISC-V microprocessors. The critical flip-flops are obtained by calculating the Architectural Vulnerability Factor (AVF) using several different processor workloads upon injection of Single-Event-Upset (SEU) faults. The impact of selective hardening on the RISC-V cores is assessed by comparing power, performance and area (PPA) metrics.

Bio

Darek Palubiak received the PhD degree in 2016 from McMaster University, Hamilton, Ontario, Canada for his work on CMOS single photon sensors. From 2015-2017 Darek worked at Envirosen, a startup company in Toronto Canada designing CMOS image sensor chips. In 2017 he joined SensL in Cork, Ireland to lead their development of CMOS LIDAR sensors. Following acquisition by Onsemi in 2018, his role expanded to include management of Functional Safety activities. In July 2021 Darek joined Cadence Design Systems in Cork where he is currently developing verification methodologies for security and safety applications.

Daniele Rossi – HW-SW Interface for RAS in RISC-V Architectures

Daniele Rossi (University of Pisa, Pisa, Italy) , Nicasio Canino, Stefano Di Matteo, Sergio Saponara.

Poster #16 in MR05-06 on Tue 6th. Links: extended abstract, poster.

Summary

System Reliability, Availability and Serviceability (RAS) are major properties in any High Performance Computing systems. An essential feature to improve RAS is represented by facilities to log hardware errors information and report it to system software. We present here the main characteristics of a HW-SW interface that we have developed to improve RAS of RISC-V architectures. We describe the main building blocks of the proposed peripheral that can be adopted in both 32- and 64-bit RISC-V architectures, their main characteristics, and the set of registers that are used to log and report main error information. Finally, an FPGA-based test platform developed to validate the proposed RAS peripheral is briefly discussed.

Warren Chen – Latency Reduction in a System with IOPMP

Warren Chen (Andes Technology, Hsinchu, Taiwan) , Paul Shan-Chyun Ku.

Poster #17 in MR05-06 on Tue 6th. Links: extended abstract, poster.

Summary

When people talk about platform security, memory isolation is considered a key fundamental. In a RISC-V-based platform, there are a couple of mechanisms inside a hart to perform physical memory isolation, such as PMP, ePMP, sPMP, etc. They are used to control the access from the CPU itself. Other than CPU, I/O agents’ accesses are controlled by IOPMP. IOPMP is a checker with a set of ordered rules. Checking an access can be time-consuming because the check may not finish in one cycle, and sometimes more than one access is needed for one check. This creates a problem for latency-sensitive systems. This document will introduce two features to mitigate this problem, which were discussed in the RISC-V IOPMP Task Group. We will first introduce the latency reduction in respect of the downstream devices of an IOPMP, and then we will discuss the cooperation between IOPMP and its upstream prefetcher.

Karim Ait Lahssaine – Memory Authenticated Encryption Engine for a RISC-V processor

Karim Ait Lahssaine (Cea, Grenoble, France) , Olivier Savry.

Poster #18 in MR05-06 on Tue 6th. Links: extended abstract, poster.

Summary

In this paper, we present the Memory Authenticated Encryption Engine (MAEE) hardware countermeasure to ensure the confidentiality and authenticity of data in RAM and the associated interconnect bus. Using the Subterranean 2.0 authenticated encryption algorithm, data used by a processor is secured at the output of cache memory, and stored in memory as chunks, containing encrypted data and metadata for authenticity verification. The MAEE provides protection against attacks targeting the memory and its bus, such as Rowhammer, fault injections or side-channel attacks. We are also evaluating the performance of this countermeasure, by associating it with the RISC-V CVA6 application core.

Franz Fuchs – Mitigating Transient-Execution Attacks with CHERI Compartments

Franz Fuchs (University Of Cambridge, Cambridge, United Kingdom) , Jonathan Woodruff, Peter Rugg, Simon W. Moore.

Poster #19 in MR05-06 on Tue 6th. Link: extended abstract.

Summary

We propose to use and extend CHERI compartments in order to mitigate transient-execution attacks. These attacks have presented a major threat in recent years, driving deployment of software mitigations and research into hardware solutions. We envision that the additional state provided by CHERI capabilities and compartments presents a viable way to solve transient-execution attacks on an architectural level. In this poster, we want to show how we can extend and use the CHERI protection model for that.

Bio

Franz Fuchs is a second-year PhD student at the University of Cambridge Department of Computer Science and Technology supervised by Prof. Simon Moore. He has a broad interest in security with his research focus on transient-execution attacks. Franz has engaged in research to conduct attacks on a superscalar, out-of-order CHERI processor and concentrates currently on defence mechanisms for capability machines. He is leading the efforts for enforcing compartmentalisation in microarchitectures within the CHERI-RISC-V project. Franz received the MSc degree in Computer Science from KTH Royal Institute of Technology and the BSc degree in Informatics from Technical University of Munich.

Abdoulaye Berthe – RISC-V Trusted MCU for Functional Safety Applications

Abdoulaye Berthe (Low Power Futures, Toronto, Canada)

Poster #20 in MR05-06 on Tue 6th. Link: extended abstract.

Summary

This paper presents a RISC-V Trusted microcontroller unit (MCU) architecture for functional safety applications. The proposed architecture targets both ASIC and FPGA implementations. The architecture is based on asymmetrical dual core configuration to enable efficient power saving and hardware isolation mechanisms to support Trusted Execution Environment (TEE) and integrated Secure Element (SE). The application core in the architecture implements various reliability and redundancy features including, protocol hardening, fault detection and alerts. Bus protocol hardening, fault detection and parity check on memories have been extended to the entire architecture to ensure reliable operations across the MCU. The architecture also includes a security engine with advanced cryptographic services and secure key management using a Physical Unclonable Function.

Bio

Dr. Berthe has a Ph. D. in Wireless Communication with more than 10 years of industry experience. Since 2020 he has been working with Low Power Futures to design and implement low power wireless baseband processors and efficient hardware acceleration engines for resource-constrained RISC-V IoT endpoints.

Luis Felipe Rojas Muñoz – Root of Trust Components to Increase Security of RISC-V Based Systems on Chips

Luis Felipe Rojas Muñoz (Imse-cnm (CSIC/Universidad de Sevilla), Sevilla, Spain) , Macarena Cristina Martínez Rodríguez, Santiago Sánchez Solano, Piedad Brox Jiménez.

Poster #21 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

This work presents the design and validation of a compact and efficient RO-PUF/TRNG module, which combines ID generation and entropy source functionalities, and can be used as an essential primitive of a hardware RoT for RISC-V based SoCs. The design was encapusalted as an IP core to provide it with a high level of configurability, flexibility, and reusability. A comprehensive SDK for online characterization, validation, and performance monitoring of PUF and TRNG quality metrics was also developed. The experimental results show that the proposed RO-PUF/TRNG IP is suitable for increasing the security of IoT applications.

Bio

Luis Felipe Rojas Muñoz is an Electronics Engineer who graduated from the Universidad Industrial de Santander, Colombia in 2015. He obtained a Master’s and PhD degree in Electrical Engineering from the University of Guanajuato, Mexico, in 2017 and 2022, respectively. Currently, he serves as a Post-Doctoral Researcher at the Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla). His scientific contributions include 5 journal papers and 3 conference presentations, focusing on FPGA-based embedded systems, evolutionary computing, cryptographic systems, and their applications in image processing and security.

Marcel Sarraseca – SafeLS: Toward Building a Lockstep NOEL-V Core

Marcel Sarraseca (Barcelona Supercomputing Center, Barcelona, Spain) , Sergi Alcaide, Francisco Javier Fuentes, Juan Carlos Rodríguez, FENG CHANG, Ilham Lasfar, Ramon Canal, Francisco J Cazorla, Jaume Abella.

Poster #22 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

Safety-critical systems such as those in automotive, avionics and space, require appropriate safety measures to avoid silent data corruption upon random hardware errors such as those caused by radiation and other types of electromagnetic interference. Those safety measures must be able to prevent faults from causing the so-called common cause failures (CCFs), which occur when a fault produces identical errors in redundant elements so that comparison fails to detect the errors and a failure arises. The usual solution to avoid CCFs in CPU cores is using lockstep cores, so that two cores execute the same flow of instructions, but with some time staggering so that their state is never identical and faults can only lead to different errors, which are then detectable by means of comparison. This paper extends Gaisler’s RISC-V NOEL-V core with lockstep; and presents future prospects for its use and distribution.

Bio

Marcel Sarraseca holds a BS in Computer Engineering (2023) from the Autonomous University of Barcelona (UAB) and currently studying MS in Innovation and Research in Informatics from Universitat Politècnia de Catalunya (UPC). Marcel Sarraseca is a junior researcher at Barcelona Supercomputing Center (BSC) in the CAOS group from the Computer Science department. He is currently involved in European projects related to safety-critical systems and functional safety, such as NimbleAI and FRACTAL.

Francisco Javier Fuentes – SafeTI Traffic Injector Enhancement for Effective Interference Testing in Critical Real-Time Systems

Francisco Javier Fuentes (Barcelona Supercomputing Center, Barcelona, Spain) , Raimon Casanova, Sergi Alcaide, Jaume Abella.

Poster #23 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

Safety-critical domains, such as automotive, space, and robotics, are adopting increasingly powerful multicores with abundant hardware shared resources for higher performance and efficiency. However, mutual interference due to parallel operation within the SoC must be properly validated. Recently, the SafeTI traffic injector has been released and integrated in a homogeneous RISC-V multicore for testing, otherwise untestable casuistic for software-only solutions. This paper introduces some enhancements performed on the SafeTI, which include internal pipelining for higher-rate traffic injection, and its tailoring to multiple interfaces, as well as its integration in a more powerful heterogeneous RISC-V multicore based on Gaisler’s technology for the space domain.

Bio

Francisco Fuentes holds degrees of BS (2018) and MS (2022) in Telecommunication Engineering from Universitat Autònoma de Barcelona (UAB) and is starting his Ph.D. Francisco Fuentes has started recently his Ph.D based on the research of traffic injectors in safety-critical systems for functional safety validation. He is a researcher at Barcelona Supercomputing Center (BSC) in the CAOS group from the Computer Science department. He has experience on the development of a RISC-V RV32IMF processor core RTL design, validation and prototyping in both simulation and FPGA environments.

Caaliph Andriamisaina – SECURE PLATFORM FOR ICT SYSTEMS ROOTED AT THE SILICON MANUFACTURING PROCESS

Caaliph Andriamisaina (Cea, List, Palaiseau, France) , Farhat Thabet, Jean-Roch Coulon, Guillaume Chauvon, Alejandro Cabrera Aldaya, Nicola Tuveri, Macarena C. Martinez-Rodriguez, Piedad Brox.

Poster #24 in MR12-13-14 on Tue 6th. Link: extended abstract.

Summary

The digital transformation is accelerating and requires the design of secure and privacy-enhancing technologies to guarantee trust on electronic devices that support it. In this context, it is designed a platform that integrates a hardware dedicated Root-of-Trust and a RISC-V processor core with the capability of offering a full suite of security services. The platform will be able to leverage this capability to support cryptographic protocols, privacy respectful attestation mechanisms, and enable trusted communication channels across 5G network infrastructures.

Helmut Kurth – Security Evaluation of a RISC-V-based SoC

Helmut Kurth (atsec GmbH) , Rasma Araby, Cheng Jiang.

Poster #25 in MR12-13-14 on Tue 6th.

Matteo Sonza Reorda – Self-Test Libraries for RISC-V safety-critical applications: recent advances

Matteo Sonza Reorda (Politecnico di Torino) , Riccardo Cantoro, Josie Esteban Rodriguez Condia, Annachiara Ruospo, Ernesto Sanchez.

Poster #26 in MR12-13-14 on Tue 6th. Link: extended abstract.

Summary

RISC-V adoption is rapidly expanding even to safety-critical application areas, such as automotive, space, robotics, and health-care. In these areas, it is crucial to guarantee that the probability of a critical failure stemming from a permanent hardware fault falls below a given threshold, often following the guidelines and rules of standards and regulations. In this scenario, possible solutions must combine functional safety goals with constraints related for example to the hardware and performance overhead, the flexibility, the ease of adoption. In the last decade, Self-Test Libraries (STLs) became a commonly adopted solution widely supported by semiconductor, IP and EDA companies, allowing system companies to deploy effective in-field test mechanisms able to detect a high percentage of permanent hardware faults arising during the operational phase (e.g., due to aging). This paper summarizes the latest advancements in the area of STLs for RISC-V architectures, emphasizing the advantages stemming under this perspective from the open instruction set architecture.

Bio

Matteo SONZA REORDA received the MSc degree in electronics and the Ph.D. degree in Computer Engineering (both from Politecnico di Torino, Italy) in 1986 and 1990, respectively. Currently, he is a Full Professor with the Department of Control and Computer Engineering of the same institution. He published more than 400 papers in the area of test and fault tolerant design of reliable circuits and systems, receiving several Best Paper Awards at major international conferences. He is involved in numerous research projects with companies and other research centers worldwide. He is a Fellow of the IEEE.

Jonas Schupp – Silicon Proven Hardware Acceleration of Post-Quantum Cryptography on RISC-V

Jonas Schupp (Technical University Of Munich, Munich, Germany) , Patrick Karl, Georg Sigl.

Poster #27 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

Hardware/Software co-designs offer a promising way to support different Post-quantum cryptographic algorithms on one platform. Especially, as these algorithms are not yet standardized, the flexibility of such an approach is important to support possible future algorithm changes in the standardization process. To explore the design space of such RISC-V based HW/SW co-designs, we present three different ASICs, designed since 2020, accelerating different subsets of the PQ-algorithms in the NIST competition, one in UMC 65nm and two in Globalfoundries‘ 22nm. All designs offer significant performance advantages over pure software implementations on the same platform, while largely maintaining the flexibility of a pure software approach.

Bio

Since 2021, Jonas Schupp is a doctoral candidate at the Chair of Security in Information Technology of Prof. Sigl at the Technical University of Munich. His main interests are on one hand the efficient and side-channel protected implementation of post-quantum cryptographic algorithms in hardware and in software, mainly on RISC-V platforms and on the other hand the evaluation and mitigation of mircoarchitectural leakage, with a focus on hardware based countermeasures. He did a successful tapeout of a Pulpino based RISC-V microcontroller with hardware accelerators for Post-Quantum Cryptography in Globalfoundries’ 22nm technology.

Li Lu – Simulation-based Fault Injection on Ibex Core with UVM Environment

Li Lu (IHP-Leibniz-Institut für innovative Mikroelektronik, Frankfurt Oder, Germany) , Junchao Chen, Markus Ulbricht, Milos Krstic.

Poster #28 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

This paper presents a procedure for implementing simulation-based fault injection on the Ibex core with its UVM testbench. The simulation aims to identify the critical flip-flops where faults could lead to erroneous system operation. We first select testcases for the simulation, based on their contributions to functional coverages. Then the simulation is conducted at the RTL. For each testcase, we remove the identified critical flip-flops from its fault list to reduce the number of faults we need to inject. The identified critical flip-flops are mapped from RTL to the gate level eventually. The procedure could reduce the time required by fault injection to some extent.

Bio

Li Lu received her second master’s degree in Simulation and Visualization at the Norwaigian Univerisity of Science and Technology, Norway, in 2020. She is a Ph.D. candidate at the University of Potsdam and is employed as a member of Prof. Krstic’s research group in IHP Microelectronics, Frankfurt (Oder), Germany. She received her first master’s degree in Software Engineering at the Huazhong University of Science and Technology, China, in 2009. She worked as an ASIC verification engineer in several telecommunication and semiconductor companies from 2009 to 2018. Now her research focuses on using Machine Learning to accelerate simulation-based fault injection.

Junchao Chen – The TETRISC SoC - A resilient quad-core system based on Pulpissimo

Junchao Chen (IHP - Leibniz Institute For High Performance Microelectronics, Frankfurt (Oder), Germany) , Li Lu, Markus Ulbricht, Milos Krstic.

Poster #29 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

Fault-tolerant systems are typically designed for worst-case scenarios and offer sub-optimal performance during normal operation. Configurable systems that adapt to changing circumstances can improve this situation. This paper presents a design that does just that. The TETRISC SoC is a multiprocessor system based on the Pulpissimo platform that uses various reliability sensors to operate its four cores in different performance and fault tolerance modes as needed. This adaptable solution provides optimal performance and reliability for use cases with high requirements, such as avionics or aerospace.

Bio

Junchao Chen received the Dr.-Ing degree from the University of Potsdam, Germany, in 2023, on the topic of “A Self-adaptive Resilient Method for Implementing and Managing High-reliability Processing Systems.” Since 2018, he has been a member of Prof. Milos Krstic’s “Fault-tolerance Computing” research group at IHP Microelectronics in Frankfurt (Oder), Germany. His research interests include self-adaptive fault-tolerance mechanisms, radiation-induced effects, high-reliability system design, and agile hardware development. Throughout his academic career, he has participated in several international and national research projects. He has published over 20 journal and conference papers and has been granted one patent.

Angeliki Kritikakou – Time-Bounded Error Mitigation through Dual-Core Lockstep RISC-V using HLS

Angeliki Kritikakou (University of Rennes, Irisa, INRIA) , Pegdwende Romaric Nikiema, Marcello Traiola, Olivier Sentieys.

Poster #30 in MR 12+13+14 on Tue 6th.

Summary

Real-time safety-critical embedded system must guarantee both reliable and in-time execution. The increasing complexity of embedded systems, alongside with the technology size reduction, makes modern processors more vulnerable to faults. Faults can impact not only the functional correctness of the application, but also the timing correctness, which is of paramount importance for safety-critical systems. To expose the fault impact, we enhance vulnerability analysis to include not only functional, but also timing correctness, and show that faults impact Worst-Case Execution Time (WCET) estimations. Common techniques to deal with faults, such as watchdog timers and re-execution, have large timing overhead for error detection and correction. As a remedy, we design reliable RISC-V cores using High Level Synthesis (HLS) with two mechanisms that perform lock-step execution with bounded WCET overhead.

Bio

Angeliki Kritikakou is an Associate Professor at University of Rennes, France, and IRISA - Inria centre at Rennes University since 2014. She obtained the HDR from University of Rennes, France, in 2022. She received the Ph.D. degree from the Dep. Electrical and Computer Engineering, Univ. Patras, Greece, in collaboration with IMEC Research Center, Belgium, in 2013, and her M.Sc degree from Dep. Electrical and Computer Engineering, Univ. Patras, Greece, in 2009. She is the scientific responsible of ANR JCJC FASY research project. Her research interests include embedded system design, reliability, real-time systems, design space exploration methodologies and run-time management techniques.

Junchao Chen – Towards High-Reliability Systems Design using Agile Hardware Development Flow

Junchao Chen (IHP-Innovations for High Performance Microelectronics, Frankfurt Oder, Germany) , Li Lu, Markus Ulbricht, Milos Krstic.

Poster #31 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

As transistor scaling continues to reach the deep nanometer range, modern systems face increasing challenges in ensuring reliability, particularly in safety- and mission-critical applications. Concurrently, the agile hardware development methods are gaining traction over the conventional waterfall approach in reducing hardware development costs. Therefore, investigating the intersection of highly reliable system design and agile hardware development processes is crucial. In this paper, we propose an iterative agile hardening strategy that integrates fault injection, reliability analysis, and hardening method selection. The proposed approach enables quick deployment of appropriate hardening methods and avoids over- or under-protection of the target system. Our goal is to achieve fine-grained high-reliability hardware development at a high abstraction level while balancing the trade-off between reliability, time-to-market, performance, and other important factors.

Bio

Junchao Chen received the Dr.-Ing degree from the University of Potsdam, Germany, in 2023, on the topic of “A Self-adaptive Resilient Method for Implementing and Managing High-reliability Processing Systems.” Since 2018, he has been a member of Prof. Milos Krstic’s “Fault-tolerance Computing” research group at IHP Microelectronics in Frankfurt (Oder), Germany. His research interests include self-adaptive fault-tolerance mechanisms, radiation-induced effects, high-reliability system design, and agile hardware development. Throughout his academic career, he has participated in several international and national research projects. He has published over 20 journal and conference papers and has been granted one patent.

Zaruba Florian – Next-Generation Edge AI Solutions built on RISC-V

Zaruba Florian (Axelera AI / OpenHW Group, Zürich, Switzerland)

Poster #32 in MR12-13-14 on Tue 6th.

Joaquim Maria Castella Triginer – Enhancing Safety with RISC-V-based SPIDER Autonomous Robot: A Use-Case from the ECSEL FRACTAL Project

Joaquim Maria Castella Triginer (Virual Vehicle Research Gmbh, Graz, Austria) , Joaquim Maria Castella Triginer, Helio Fernandez, FENG CHANG, Sergi Alcaide, Ramon Canal, Jaume Abella.

Poster #33 in MR12-13-14 on Tue 6th. Link: extended abstract.

Summary

The SPIDER use case of the ECSEL FRACTAL project demonstrates the safety capabilities developed in the project on a RISC-V platform. The use case demonstrates the integration of a diverse redundancy service and a multicore interference monitoring service. These services allow the SPIDER co-execution of safety-relevant and machine learning tasks, while implementing fail-operational capabilities on a single computing device.

Bio

Joaquim M. Castella Triginer is a researcher in functional Safety, Cybersecurity and SOTIF for automotive and Railway topics at the Dependable Systems group in Virtual Vehicle. He studied Computer Systems and Industrial Engineering at the Polytechnic University of Catalonia and Automotive Engineering at FH Joanneum Graz. His main research interests include safety and cybersecurity analysis, vehicle architecture design, and verification and validation methods.

Sandro Pinto – CROSSCON: Interoperable IoT Security Stack - The RISC-V Opportunity

Sandro Pinto (Universidade do Minho, Guimaraes, Portugal) , Matjaz Breskvar, Tiago Gomes, Hristo Koshutanski, Aljosa Pasic, Piotr Krol, Emna Amri, David Puron, Zoltan Hornak, Marco Rovieri, Alexandra Dmitrienko, Ahmad-Reza Sadeghi, Bruno Crispo.

Poster #34 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

CROSSCON is a 3-year, multi-million euro, Research and Innovation Action funded under Horizon Europe. The project aims to design a new open, modular, highly portable, and vendor-independent IoT security stack that can run on various devices using heterogeneous hardware architectures, including RISC-V. The Consortium sees in RISC-V a two-fold opportunity. Firstly, by aiming to develop an interoperable reference security stack, we believe we can contribute to the expected specifications of ongoing initiatives for Trusted Execution and Confidential Computing on Application processors (i.e., CoVE) and microcontrollers. Secondly, RISC-V offers a unique opportunity to develop novel security hardware extensions for software services, either by creating extensions directly to the ISA or developing non-ISA hardware mechanisms that support the efficient implementation of security guarantees at the application level.

Wolfgang Ecker – Scale4Edge – Scaling RISC-V for Edge Applications

Wolfgang Ecker (Infineon Technologies) , Milos Krstic, Markus Ulbricht, Andreas Mauderer, Eyck Jentzsch, Andreas Koch, Bastian Koppelmann, Wolfgang Mueller, Babak Sadiye, Niklas Bruns, Rolf Drechsler, Daniel Mueller-gritschneder, Jan Schlamelcher, Kim Grüttner, Jörg Bormann, Wolfgang Kunz, Reinhold Heckmann, Gerhard Angst, Ralf Wimmer, Bernd Becker, Tobias Faller, Paul Palomero Bernardo, Oliver Bringmann, Johannes Partzsch, Christian Mayr.

Poster #35 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

The Scale4Edge project is focused on enabling an effective RISC-V ecosystem for optimization of edge applications. The main objective of the project is the development of an ecosystem, based on a platform concept, to supply efficient and cost-effective application-specific edge devices and value-added services addressing different market segments. This is achieved through the automatic and very fine-grained adaptation of highly generic components to the application. The Scale4Edge ecosystem covers highly scalable components and tools and extends them for application-specific edge components at three levels: (1) CPU instruction level defined by the RISC-V Instruction Set Architecture (ISA), (2) software level defined by the C programming language standard C11 with compilers and libraries open to complementary standards like MISRA-C, and (3) operating system and firmware level through system services, configuration interfaces, and drivers.

Gerard Rauwerda – SmallSat Payload Control & Data Processing: High-Reliability and High-Security With RISC-V

Gerard Rauwerda (Technolution B.V., Gouda, Netherlands) , Camiel Vletter, Dave Marples, Marco Ottavi, Bruno Forlin, Sybren de Jong, Hans Dekker.

Poster #36 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

This work presents a Control & Data Processing Unit targeted at SmallSats which sits between a platform and its instruments. It includes a (possibly radiation-hardened) FPGA with a RISC-V softcore and optional accelerators, allowing for edge processing. This opens the door for payload control, encryption and data processing in space. The CDPU also reduces time-to-orbit by removing the need to design an instrument for a specific platform.

Bio

Dr.ir. Gerard Rauwerda is Business Developer at the leading technology integrator Technolution Advance for the metrology and data processing & analysis programme lines. He has a focus on (Big) Science and Technology, including space technology, FPGA and RISC-V. He co-founded the start-up Recore Systems in 2005, and was CTO until 2018. The fabless semiconductor company developed advanced digital signal processing platforms and licensed DSP semiconductor IP. Recore’s technology enabled ultra energy-efficient digital signal processing in streaming data analytics and fault-tolerant space applications. He holds a PhD degree in Computer Science and a MSc degree in Electrical Engineering (both from University of Twente, The Netherlands) with over 20 years’ experience in multi-core semiconductor design and signal processing architectures.

Leonidas Kosmidis – The METASAT Hardware Platform: A High-Performance Multicore, AI SIMD and GPU RISC-V Platform for On-board Processing

Leonidas Kosmidis (Barcelona Supercomputing Center (BSC), Barcelona, Spain) , Marc Solé I Bonet, Jannis Wolf, Ivan Rodriguez Ferrández, Matina Maria Trompouki.

Poster #37 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

The METASAT Horizon Europe project which is funded by the European Commission and started in January 2023, will enable model-based design methodologies in order to manage the complexity of upcoming hardware and software for space on-board processing. As a representative high performance platform for on-board processing, METASAT will design a multicore platform featuring accelerators prototyped on an FPGA. This includes both an AI SIMD accelerator tightly integrated with the CPU, as well as a GPU. All hardware components of the METASAT platform will be open source and based on the RISC-V open ISA. In this abstract, we provide an overview of the platform architecture as well as preliminary implementation decisions and the current development status.

Bio

Dr. Leonidas Kosmidis is a Senior Researcher at the Barcelona Supercomputing Center (BSC) and the Universitat Politècnica de Catalunya (UPC). He holds a PhD in Computer Architecture from UPC and a BSc in Computer Science from University of Crete. He is leading the research on embedded GPUs for safety critical systems, both at hardware and system software level within the CAOS (Computer Architecture/Operating Systems) group. He is the PI of several projects funded by the European Space Agency (ESA) such as the GPU4S (GPU for Space) and the Horizon Europe METASAT project, as well as projects funded by industry such as the Airbus Defence and Space which focus on the adoption of GPUs in space and avionics systems. He is also participating in several standardisation efforts regarding GPU programming in safety critical systems. Dr. Kosmidis is the recipient of the RISC-V Educator of the Year Award in 2019 from the RISC-V Foundation and an Honourable Mention for the EuroSyS Roger Needham PhD Award in 2018.

Juan Fumero – Harnessing Hardware Acceleration with RISC-V and the EU Processor

Juan Fumero (The University Of Manchester, Manchester, United Kingdom) , Athanasios Stratikopoulos, Mehdi Goli, Ruyman Reyes, Konstantinos Nikas, Dionisios Pnevmatikatos, Nectarios Koziris, Christos Kotselidis.

Poster #38 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

In this talk, we will present the newly EU-funded project AERO (Accelerated EU Cloud) whose mission is to bring up and optimize the software stack of cloud deployments on top of the EU processor. After providing an overview of the AERO project, we will expand on two main components of the software stack to enable seamless acceleration of various programming languages on RISC-V architectures; namely, ComputeAorta which enables the generation of RISC-V vector instructions from SPIR-V binary modules, and TornadoVM which enables transparent hardware acceleration of managed applications. Finally, we will describe how the ongoing integration of ComputeAorta and TornadoVM will enable a plethora of applications from managed languages to harness RISC-V auto-vectorization completely transparently to developers.

Bio

Juan Fumero is a Research Fellow working as part of the Advanced Processor Technologies (APT) Research Group at The University of Manchester on Heterogeneous Virtual Machines and language runtime systems for the acceleration of applications using Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). He is also the software architect of the TornadoVM project. Currently, he collaborates with Intel to bring oneAPI into the TornadoVM framework to perform optimisations for Intel compute architectures (xPUs). He is also an Intel Innovator, and he participates in the Level Zero Technical Advisory Board for helping to shape the next versions of the Level Zero APIs for managed runtime programming languages.

Jeremy Bennett – The CORE‑V software ecosystem: Ten lessons learned from developing vendor specific compiler tool chains

Jeremy Bennett (Embecosm, Southampton, United Kingdom)

Poster #39 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

CORE-V is a family of RISC-V processor cores available as free silicon IP from the Open Hardware Group (abbreviated here as OpenHW Group). The OpenHW Group is a consortium of 102 industrial, academic and other organizations creating free and open source RISC-V IP that is verified and commercially robust. The CORE-V family makes heavy use of both non-standard and standard ISA extensions. In this talk we look at the challenges is creating the software tool chains to go alongside this silicon IP and present a series of lessons learned. This talk is illustrated by reference to both GCC and Clang/LLVM tool chains for CORE-V, particularly the 32-bit CV32E40Pv2 processor.

Bio

Jeremy Bennett is Chief Executive of Embecosm, a consultancy specializing in complex open source software, best known for its work on compilers, processor modeling and AI/ML. He is also Chair of the Software Task Group of the Open Hardware Group. Dr Bennett is author of the standard textbook “Introduction to Compiling Techniques” (McGraw-Hill 1990, 1995, 2003). He holds an MA and PhD from the University of Cambridge.

Pierre Ravenel – A gem5-based CVA6 Framework for Microarchitectural Pathfinding

Pierre Ravenel (Kalray, Grenoble, France)

Poster #40 in MR12-13-14 on Tue 6th. Links: extended abstract, poster.

Summary

Succesfully designing a well-balanced general purpose processor targeting an ASIC implementation is an arduous task. As a result, software timing models are generally developped to enable fast design space exploration in the pathfinding phase. Those models are later tightly correlated to RTL as it becomes available, but can still provide valuable insight late in the design phase as they can simulate large workloads and provide non-intrusive access to internal information. In this paper, we leverage the gem5 timing simulator infrastructure to provide a fast timing simulation environment to drive microarchitectural improvements for the risc-v CVA6 processor. We also depict a correlation flow to ensure that the timing performance model keeps projecting meaningful performance numbers.

Posters on Display Wednesday June 7th

Presenters are expected to be with their poster during the morning break, lunch and afternoon break.

William PENSEC – When in-core DIFT faces fault injection attacks

William PENSEC (University Southern Brittany, Lorient, France) , Vianney Lapôtre, Guy GOGNIAT.

Poster #1 in MR07-08 on Wed 7th. Links: extended abstract, poster.

Summary

Both software and physical attacks are serious threats for Internet of Things (IoT) devices. Low-cost and low-power processors are usually the key component of these systems. They manipulate sensitive data leading to strict security needs. In this paper, we study the impact of Fault Injection Attacks (FIA) on protected RISC-V processor integrating a Dynamic Information Flow Tracking (DIFT) mechanism against software threats.

Bio

William PENSEC received his MSc in Computer Science with a specialisation in Software for Embedded Systems from Université de Bretagne Occidentale (UBO), in Brest, France in 2021. He joined the ARCAD team at the Lab-STICC laboratory in France starting his PhD in 2021 in Hardware Security at the Université Bretagne Sud in Lorient, France. His area of research focuses on embedded system security, RISC-V core, fault injection attacks, in order to protect a RISC-V core against both software and physical attacks.

Sylvain Lefebvre – Iron: Selectively turn RISC-V binaries into hardware co-processors.

Sylvain Lefebvre (Inria, Villers-les-nancy, France)

Poster #2 in MR07-08 on Wed 7th. Links: extended abstract, poster.

Summary

We explore whether already compiled RISC-V binaries can be selectively turned into hardware. From a list of function symbols selected by the designer, Iron automatically generates a hardware design consisting of a SOC and RISC-V CPU, together with co-processors synthesized from the selected functions machine code. Whenever the CPU reaches the address of one of these functions, the corresponding co-processor executes instead. This makes the change from the software to the hardware versions completely seamless, enabling client-side hardware acceleration, possibly depending on available hardware resources (e.g. various FPGAs). RISC-V is particularly well suited to this endeavor thanks to its wide adoption, reduced instruction set, many registers and clean open-source ISA. We discuss a proof of concept, the encountered challenges and the excitingvenues for future work. Iron is an open-source software.

Bio

Sylvain Lefebvre is a senior researcher at Inria, France, where he leads the MFX team. His work focuses on algorithms for generating and processing complex shapes in Computer Graphics and additive manufacturing, using CPUs, GPUs and FPGAs. Sylvain received the Eurographics young researcher award in 2010, an ERC starting researcher grant in 2012 (Shapeforge) and an ERC proof of concept grant in 2015 (IceXL). He started the MFX research team in 2018. Sylvain is the creator and lead developer of the IceSL software for 3d printing and the Silice language for hardware design. In his spare time, he enjoys exploring retro Computer Graphics algorithms, as well as making and hacking things.

Roddy Urquhart – Unlocking the potential of RISC-V with HW/SW co-design

Roddy Urquhart (Codasip)

Poster #3 in MR07-08 on Wed 7th. Links: extended abstract, poster.

Summary

The RISC-V architecture was created to cover a wide range of applications. With a good base integer set, optional standard extensions and a defined approach to custom instructions the RISC-V ISA is well equipped to handle an enormous variety of computational tasks. To date, the majority of the R & D effort into RISC-V cores has been focused on essentially replacing well known cores from legacy proprietary architectures. With semiconductor scaling slowing if not failing, the main way to achieve improved performance efficiently is with architectural innovation. A wide range of specialized applications is well-suited to the RISC-V ISA but require specialized processor cores. To meet ongoing demands a larger number of custom processor cores are needed but there are a limited number of processor design engineers. This demand can be met by both reducing the design cycle through processor design automation technology and by using existing RISC-V processor cores as a starting point for customization.

Karan Pathak – Validating Full-System RISC-V Simulator: A Systematic Approach

Karan Pathak (Tu Delft/EPFL, Lausanne, Switzerland) , Joshua Klein, Giovanni Ansaloni, Marina Zapater, David Atienza.

Poster #4 in MR07-08 on Wed 7th. Links: extended abstract, poster.

Summary

RISC-V-based Systems-on-Chip (SoCs) are witnessing a steady rise in adoption in both industry and academia. However, the limited support for Linux-capable Full System-level simulators hampers development of the RISC-V ecosystem. We address this by validating a full system-level simulator, gXR5 (gem5-eXtensions for RISC-V), against the SiFive HiFive Unleashed SoC, to ensure performance statistics are representative of actual hardware. This work also enriches existing methodologies to validate the gXR5 simulator against hardware by proposing a systematic component-level calibration approach. The simulator error for selected SPEC CPU2017 applications reduces from 44% to 24%, just by calibrating the CPU. We show that this systematic component-level calibration approach is accurate, fast (in terms of simulation time), and generic enough to drive future validation efforts.

Bio

Mr. Karan Pathak is pursuing Master’s in Embedded Systems at TU Delft. He is currently a visiting student at EPFL, working towards his Master Thesis at Embedded Systems Lab. His research interests include Computer Architecture and Real-time Systems. His research stint at EPFL is funded by Justus and Louise van Effen research grant.

Nick Brown – Experiences of running an HPC RISC-V testbed

Nick Brown (Epcc At The University Of Edinburgh, Edinburgh, United Kingdom) , Maurice Jamieson, Joseph Lee.

Poster #5 in MR07-08 on Wed 7th. Links: extended abstract, poster.

Summary

Funded by the UK ExCALIBUR H&ES exascale programme, in early 2022 a RISC-V testbed for HPC was stood up to provide free access for scientific software developers to experiment with RISC-V for their workloads. Here we report on successes, challenges, and lessons learnt from this activity with a view to better understanding the suitability of RISC-V for HPC and important areas to focus RISC-V HPC community efforts upon.

Bio

Dr Nick Brown is a Research Fellow at EPCC the University of Edinburgh with interests in HPC application development, novel heterogeneous architectures, data science, programming language design, and compilers. He has worked on several large-scale parallel codes and is interested in the role of novel architectures, such as RISC-V and FPGAs, for accelerating HPC codes in a power efficient manner as well as how we can encode algorithmic patterns into the compiler to hide much of the required complexity porting between technologies. He leads EPCC’s RISC-V testbed which aims to provide access to this technology for scientific software developers and is the knowledge exchange coordinator on the xDSL project which leverages MLIR/LLVM for a common Domain Specific Language ecosystem. Nick is a course organizer on EPCC’s MSc in HPC and data science courses, as well as supervising MSc and PhD students.

Ayoub Mouhagir – Exploring RISC-V based platforms within VPSim simulation tool for High Performance Computing

Ayoub Mouhagir (Paris-Saclay University, CEA, List, Paris, France) , Mohamed Benazouz, Lilia Zaourar.

Poster #6 in MR07-08 on Wed 7th. Link: poster.

Summary

The RISC-V Instruction Set Architecture has gained much attention recently due to its open-source nature, flexibility, and greater customization. RISC-V-based platforms are becoming increasingly popular in the embedded systems industry. However, designing and implementing such systems could take time and effort. In order to address these challenges, virtual prototyping tools are widely adopted so that designers can model, simulate, test, and optimize their complex systems in early design phases. VPSim is a tool developed to speed up the SW/HW co-validation of various computer architectures, including RISC-V-based systems.

Bio

Ayoub Mouhagir received his engineer degree in Embedded Electronics from ENSEIRB-MATMECA Bordeaux, France in 2020. He joined CEA, Paris saclay as a research engineer in 2021. Currently part of the Laboratory of Architectures and Design Environment (LECA) at the CEA List Institute, contributing to the EDA (Electronic Design Automation) activity team. With his academic background, Ayoub brings comprehensive knowledge in both hardware and software domains. He actively contributes to the development of VPSim, a Virtual Prototyping tool, within the European Processor Initiative (EPI). His research interests encompass innovative design methodologies and tools for simulation, exploration, and performance evaluation for High-Performance Computing (HPC) and automotive architectures."

Xabier Abancens Calvo – Extending OpenPiton framework towards the HPC domain: first steps

Xabier Abancens Calvo (Barcelona Supercomputing Center (BSC), Barcelona, España) , Mohsin Shahbaz, Teresa Cervero Garcia.

Poster #7 in MR07-08 on Wed 7th. Links: extended abstract, poster.

Summary

HPC applications are demanding more specialized accelerators to tackle with their increasing complexity, and requirements. This context, together with the fact that Europe is promoting the use of the open source RISC-V ISA, brings the opportunity of exploring the design space for specific working scenarios. For research and exploration purposes, OpenPiton could be a well-suited framework for future manycore accelerators designs, although there are several areas that should be improved to achieve HPC performance. This paper presents an extension of the OpenPiton framework towards the HPC domain, starting from modifying the computational elements, the Tiles. In addition, this paper extends the SystemVerilog verification environment, but also the FPGA implementation.

Bio

Xabier Abancens got his Master in Telecommunication Engineering in 2013 by the University of Navarra. After that he worked as hardware engineer in different institutions, such as the Franunhofer ISS, and Alor Tech. In 2022 he joined Barcelona Supercomputing Center, and since that he has been working in the MEEP project as RTL team leader.

Umair Riaz – MEDEA: Improved Memory-Level Parallelism in a decoupled execute/access vector accelerator

Umair Riaz (Barcelona Supercomputing Center, Barcelona, Spain) , Luis A. Plana, Peter Wilson, John Davis.

Poster #8 in MR07-08 on Wed 7th. Links: extended abstract, poster.

Summary

The performance of Machine learning and graph-based applications is hampered by the inefficient use of memory bandwidth caused by their sparse access patterns. In order to improve bandwidth utilization in a RISC-V based vector accelerator, the Memory Engine for Decoupled Execute/Access (MEDEA) combines a hardware engine that handles vector loads and stores efficiently with a dedicated core that supports memory-intensive operations such as spinlocks and memcpy. Although work on MEDEA is still in progress, simulations show that it can have a large impact on the performance of sparse-memory applications such as SpMV.

Bio

Umair Riaz is an RTL Design Engineer at Barcelona Supercomputing Center, working within European Exascale Accelerator (EEA) group mainly focused on using RISC-V ISA. He has been working across RISC-V hardware design for a couple of years. He holds a bachelor’s degree in Electronic Engineering from the University of Engineering and Technology (UET), Taxila, Pakistan, in 2018. Since then, he has joined the hardware design industry, working around digital systems targeting FPGA and ASIC. Most of his work has been around developing the RTL of digital designs, including RISC-V-based processors.

Marco Bertuletti – Parallel Sparse Deep Learning Operators on Lightweight RISC-V Processors

Marco Bertuletti (ETH Zurich, Zurich, Switzerland) , Tim Fischer, Yichao Zhang, Luca Benini.

Poster #9 in MR07-08 on Wed 7th. Link: poster.

Summary

Sparsification targets both the reduction of the memory footprint and the acceleration of deep neural networks. This paper proposes a parallel implementation for key sparse Deep Learning (DL) kernels to achieve optimal performance on the Snitch Cluster, a multi-core architecture based on lightweight RISC-V processors. Our best parallel implementations achieve speed-up in a 1.1 × −7× range and a reduction in memory footprint, with respect to their dense counterpart.

Bio

Marco Bertuletti received the Bachelor’s Degree and The Master’s Degree in Electronics Engineering at Politecnico di Milano, Italy. He is now pursuing his Ph.D in Electronics Engineering at ETH Zurich, Switzerland, as a member of the Parallel Ultra Low Power (PULP) group. In his research he develops RISC-V hardware and software for wireless communications. His main interest are highly parallel multi-core and many-core processors. He also focuses on the application of Deep Learning models to 5G and 6G signal processing.

Côme Allart – Performance Modeling of CVA6 with Cycle-Based Simulation

Côme Allart (Thales DIS, Meyreuil France - Mines Saint-Etienne, CEA, Leti, Centre CMP, F - 13541 Gardanne France, Aix-en-Provence, France) , Jean-Roch Coulon, André Sintzoff, Olivier Potin, Jean-Baptiste Rigaud.

Poster #10 in MR07-08 on Wed 7th. Links: extended abstract, poster.

Summary

This paper is about CVA6 performance. We introduce a cycle-based model of CVA6 core to predict improvement of architecture modifications without modifying RTL code nor running a design frontend flow. 99.2 % accuracy has been measured. It is exploited to forecast 4.54 CoreMark/MHz for a 2-wide superscalar CVA6. Before that, we measure CVA6 CoreMark/MHz score using a CVA6 parameter to take advantage of fast memory.

Bio

Côme Allart received an engineering degree in microelectronics and computer science from the École des Mines de Saint-Étienne in 2022. He is currently a PhD student at Thales DIS, Meyreuil, France and Mines de Saint-Étienne, Gardanne, France. His research interests include microprocessor performance.

Stepan Nassyr – Programmatically Reaching the Roof: Automated BLIS Kernel Generator for SVE and RVV

Stepan Nassyr (Forschungszentrum Juelich Gmbh, Aachen, Germany) , Kaveh Haghighi Mood, Andreas Herten.

Poster #11 in MR05-06 on Wed 7th. Links: extended abstract, poster.

Summary

A novel generator is used to generate highly optimized, architecture-specific microkernels for the BLIS library. The performance of potential GEMM microkernels is evaluated on Allwinner D1, EUPILOT VEC accelerator FPGA SDV and Fujitsu A64FX.

Bio

After studying physics at the Bergische Universität Wuppertal, Stepan Nassyr joined the Juelich Supercomputing Centre in July 2017 to work on his PhD dealing with future supercomputer architectures with a focus on ARM. As part of the application oriented technology group at the Juelich Supercomputing Centre he has worked extensively with the ARM ecosystem and the ARM SVE extension, focusing mostly on hand-written assembly kernels and the requirements to the microarchitecture and memory architecture to effectively exploit the available compute capabilities in the context of HPC applications. Recently he joined the EUPILOT project to work on RISC-V RVV implementations of numerical libraries

David Ditzel – RISC-V’s revolutionary role for simultaneously supporting machine learning and HPC

David Ditzel (Esperanto Technologies Europe, S.L.U., Madrid, Spain)

Poster #12 in MR05-06 on Wed 7th. Link: extended abstract.

Summary

High-end computing is undergoing revolutionary change. After many years of most high-end computers being used to serve web pages, the last decade saw a remarkable growth in the use of machine learning. Separately, HPC computers continued to grow peak flop rates, but system design was largely constrained to x86 server CPUs coupled with GPU accelerators. The thesis of this presentation is that the rise of generative-AI system is the final tipping point that will push for merged ML/HPC system design, and that RISC-V is well positioned to be able to take a leading role in this revolution.

Eduardo Tomasi Ribeiro – Towards Simulation of an Unified Address Space for 128-bit Massively Parallel Computers

Eduardo Tomasi Ribeiro (CEA List, Grenoble, France) , César Fuguet Tortolero, Christian FABRE, Frédéric Pétrot.

Poster #13 in MR05-06 on Wed 7th. Links: extended abstract, poster.

Summary

High Performance Computing (HPC) supercomputers are composed of up to ten thousand nodes, each one having hundreds of cores organized around a shared memory. These nodes communicate through a high-performance communication network. Applications for HPC have increasing needs, both in terms of computational speed and the size of datasets to be processed. To follow these needs, memory in supercomputers is increasing at a rate such that, in the next decade, it will likely exceed 264 bytes. The RISC-V 128-bit ISA gives us the opportunity to rethink how memory is addressed and virtualized at the scale of a supercomputer. We are working on a platform to simulate a distributed 128-bit system with a global address space shared by the whole supercomputer.

Lucas Klemmer – A DSL for Visualizing Pipelines: A RISC-V Case Study

Lucas Klemmer (Johannes Kepler University Linz, Linz, Austria) , Daniel Große.

Poster #14 in MR05-06 on Wed 7th. Link: extended abstract.

Summary

The number of available RISC-V cores is growing rapidly and the openness of RISC-V enabled even smaller teams to develop their own cores. However, the wide variety of RISC-V cores available today and the high modularity of the ISA makes it hard for development tools to keep up with the speed of development, as well as to provide first class support for this growing ecosystem. In this paper, we present a Domain Specific Language (DSL) for defining processor pipelines. With just a few lines of code in this DSL, information about RISC-V pipelines can be collected from simulation waveforms for further processing. As one application of this DSL, we present a web application that functions as a pipeline rendering backend, helpful for debugging and design understanding.

Bio

Lucas Klemmer is a PhD student at the Institute for Complex Systems at the Johannes Kepler University in Linz, Austria. He received his Master’s degree in computer science from the University of Bremen in Germany. Currently, his research interests include RISC-V, verification at the HW/SW interface, and the analysis of waveforms.

Karsten Emrich – Extended Abstract: A Flexible Simulation Environment for RISC-V

Karsten Emrich (Technical University Munich, Munich, Germany) , Conrad Foik, Daniel Mueller-gritschneder, Ulf Schlichtmann, Johannes Kappes, Sebastian Prebeck, Wolfgang Ecker.

Poster #15 in MR05-06 on Wed 7th. Links: extended abstract, poster.

Summary

In this paper, we present a flexible simulation environment, well-suited for rapid prototyping of RISC-V embedded software. The environment supports both purely functional and performance simulations. It is based on an open-source instruction set simulator (ISS), called ETISS, which features a plugin mechanism to easily extend its functionality. This allows, for instance, to retrieve and modify the simulator state, enabling an early evaluation of the chosen processor architecture. Our approach utilizes this extensibility to automatically generate behavioral models for ETISS, based on abstract instruction set architecture (ISA) descriptions. This enables a quick adaptation of ETISS to an ISA variant, and eases the integration of our approach into existing design flows, e.g., to generate and validate custom RISC-V cores. We also outline how to extend ETISS to work as a performance estimator, using abstract descriptions of the targeted microarchitectures.

Bio

Karsten Emrich works as a doctoral candidate at the Chair of Electronic Design Automation at the Technical University of Munich in the Electronic System Level research group lead by Daniel Mueller-Gritschneder. He received his M.Sc. in Electrical Engineering and Information Technology in 2020 at TUM. The topic of his thesis was “Bi-Directional and Reconfigurable Power Converters for Direct Reuse of Second-Life Electric Vehicle Batteries”. His current research interests include microarchitectural behavior and performance modeling and simulation of RISC-V processors. In the past he was also active in the field of automotive hardware-in-the-loop simulation.

Jin Chufeng – A Micro Arch Design of L1 Cache for GPGPUs Supporting Release Consistency-directed Coherence Based on RVWMO

Jin Chufeng (Tsinghua University, Beijing, China) , Kexiang Yang, Jingzhou Li, He Hu.

Poster #16 in MR05-06 on Wed 7th. Links: extended abstract, poster.

Summary

Coherence and consistency are critical factors in multi-core processors and parallel programming models. In this paper, we present an RTL implementation of an L1 vector cache that supports Release Consistency-directed Coherence (RCC) based on RVWMO for open-source GPGPU, the RISC-V ISA provided consistency model. We propose a methodology for transforming axiomatic rules into hardware design guidance. Our design aims to achieve a good performance-cost trade-off for GPGPU cache design. We are currently conducting litmus tests and performance evaluations to further validate our proposed design.

Bio

Jin Chufeng is a grad student of DSPLAB from the School of Integrated Circuits, Tsinghua University. He received his Bachelor of Engineering degree from the Exemplary School of Microelectronics, University of Electronic Science and Technology of China in 2020. Jin Chufeng’s research interests include the on-chip memory systems for high performance computing, especially their microarchitecture design.

Gregory Chadwick – Developing an Open-Source Silicon Ecosystem: The Silicon Commons

Gregory Chadwick (Lowrisc Cic, Bristol, United Kingdom) , Andreas Kurth, Marno van der Maas.

Poster #17 in MR05-06 on Wed 7th. Links: extended abstract, poster.

Summary

Open-source silicon has the potential to reduce the blind-trust risk in integrated circuits (ICs) and enable reuse and collaboration on high-quality, thoroughly verified, interoperable IC blocks. RISC-V as an open standard instruction set architecture (ISA) is a key enabler for open-source silicon. The RISC-V ISA and an open-source RISC-V core alone are not sufficient to form an open-source silicon ecosystem, however: other IC blocks, such as on-chip interconnects and off-chip interfaces adhering to industry standards, are also required. While there is open-source design code for some of these blocks, practically none of them come with verification code, which is crucial for commercial silicon. The Silicon Commons is an open-source silicon ecosystem that contains design and verification code of IC blocks that form a full chip framework. The Silicon Commons also standardizes technical and organizational processes that enable multiple organizations to collaboratively engineer silicon and software that serves their mutual interests. The Silicon Commons is actively applied in the OpenTitan project.

Bio

Greg is the digital design lead at lowRISC, where he develops Ibex and works on the OpenTitan Project (an open silicon root of trust). His work at lowRISC includes SoC architecture, CPU design, security hardening and verification. He has close to 10 years experience in the silicon industry, having worked on the design of memory systems for A class CPUs at Arm and GPU design at Broadcom. He completed his Ph.D at the Cambridge Computer Laboratory (UK) in 2011 with the thesis ‘Communication centric, multi-core, fine-grained processor architecture’

Karol Gugala – Enabling Collaborative Chip Design in the RISC-V VeeR core and Caliptra RoT Project with CHIPS Alliance tools

Karol Gugala (Sweden)

Poster #18 in MR05-06 on Wed 7th.

Yifei Zhu – GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations

Yifei Zhu (RIOS Lab, Tsinghua-Berkeley Shenzhen Institute, Tsinghua University, Shenzhen, China) , Xinze Wang, Guohua Yin, Zhangxi Tan.

Poster #19 in MR05-06 on Wed 7th. Links: extended abstract, poster.

Bio

a bachelor-straight-to-doctorate student of the RISC-V International Open Source Laboratory (RIOS Lab), Tsinghua University and advised by Dr. Zhangxi Tan. Yifei Zhu received her bachlor degree in Communication Engineering, from UESTC in China. Her research interests include Computer Architecture Design, Machine Learning application in EDA

Manuel Rodríguez – Open-source RISC-V Input/Output Memory Management Unit (IOMMU) IP

Manuel Rodríguez (Centro ALGORITMI/LASI, Universidade Do Minho, Guimarães, Portugal) , Francisco Marqués Da Costa, Bruno Sá, Sandro Pinto.

Poster #20 in MR05-06 on Wed 7th. Links: extended abstract, poster.

Summary

This work describes the design and implementation of an open-source IOMMU IP compliant with the ratified version of the RISC-V IOMMU specification (v1.0-rc1). So far, we have designed and implemented a basic IP encompassing only the mandatory features (of the spec) and support for virtualization. which has been successfully validated and evaluated on a single-core CVA6-based SoC. Moving forward, we plan to extend the IP with more advanced features, i.e., optional features such as a hardware performance monitor, memory-resident interrupt files support, etc. We will open-source our IP to the RISC-V community.

Bio

Manuel Rodríguez received a Bachelor’s degree in Electronic and Computer Engineering in 2021. He is currently pursuing an M.Sc. degree working in the Embedded Systems Research Group, at the University of Minho, Portugal, specializing in the Embedded Systems and Micro/Nanotechnologies fields. His areas of interest include computer architecture, hardware design, embedded virtualization, operating systems and automotive." Contact him at pg47436@alunos.uminho.pt.

Marton Bognar – Proteus: An Extensible RISC-V Core for Hardware Extensions

Marton Bognar (imec-DistriNet, KU Leuven, Leuven, Belgium) , Job Noorman, Frank Piessens.

Poster #21 in MR12-13-14 on Wed 7th. Link: extended abstract.

Summary

We present Proteus, an open-source RISC-V processor designed to allow rapid prototyping and evaluation of hardware extensions. This goal of making it easy to extend the processor’s functionality and change its microarchitecture is enabled by making Proteus configurable in many parameters and using a plugin system for its functionality. Building on these plugins, Proteus features textbook implementations of an in-order and an out-of-order pipeline. We implement Proteus in SpinalHDL, which generates Verilog code that can run in a simulator or be synthesized to an FPGA, enabling rapid development and testing. This paper briefly introduces the processor’s design and showcases hardware security extensions implemented on Proteus.

Bio

Marton is a Ph.D. candidate at the DistriNet research group of KU Leuven under the supervision of Frank Piessens. His interest lies in the intersection of hardware design, side-channel attacks, and formal verification. He is active in offensive and defensive research, contributing to projects on side-channel attacks on commercial processors and web browsers; and building hardware extensions to protect software from speculative attacks and more.

Thomas Benz – Puma: An End-to-End Open-Source Linux-capable RISC-V SoC in 130nm CMOS

Thomas Benz (ETH Zurich, Zurich, Switzerland) , Paul Scheffler, Jannis Schönleber, Luca Benini.

Poster #22 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

Open-source architecture design and register-transfer level (RTL) descriptions, particularly around RISC-V, have made huge strides in the past decade. While open-source physical design and implementation are still lagging behind by comparison, they have recently been catching up: open EDA tools are nearing feature completeness, and some proprietary PDKs are being opened. We present Iguana, the first end-to-end open-source Linux-capable, 64-bit RV64GC, RISC-V System-on-Chip (SoC). Scheduled to tape out in IHP’s 130nm technology, which is currently being open-sourced, Iguana sets important milestones for both open-source silicon and European silicon sovereignty. It implements our Cheshire architecture, which uses IP-based high-level synthesis (iHLS) to generate SoCs from carefully designed, silicon-proven open-source IPs. It includes a variety of standard peripherals, a DRAM controller, VGA display output, and a parallel die-to-die link. Cheshire, all its IPs and physical layers (PHYs) are released under a liberal Apache-based license. We implement Iguana with a fully open RTL-to-GDS toolchain, using established tools where possible and filling gaps with our open tools. Iguana is not a one-shot, but the first in a series of SoCs we will progressively extend and improve on. Furthermore, we have pre-validated our architecture through an FPGA mapping and a tested silicon prototype in TSMC’s proprietary 65nm node.

Jérôme Quévremont – Recent Achievements of the Open-Source CVA6 Core: FPGA Optimizations, Coprocessor Acceleration, Yocto Linux Support

Jérôme Quévremont (Thales Research & Technology, Palaiseau, France) , Sébastien Jacq, Jean-Roch Coulon, Kevin Eyssartier.

Poster #23 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

In this extended abstract, recent contributions to the CORE-V CVA6 open-source RISC-V application core are presented: (1) the FPGA optimizations that reduce by 55% the resources while increasing performance by 40%; (2) the CV-X-IF coprocessor interface to extend and speed up the supported instruction set and (3) the availability of the Yocto embedded Linux distribution for 32- and 64-bit versions of the core. These contributions are available from open-source repositories and are brought to the first cooperative projects implementing the roadmap for European sovereignty on open-source hardware, software and RISC-V.

Bio

Jérôme Quévremont graduated in telecommunications and electronics in 1995 (Télécom Bretagne, now IMT Atlantique). After developing telecom and security integrated circuits at Texas Instruments and Thales Communications, in 2007 he headed a development lab, specialized in specifying, developing and validating secure- and crypto-chips in ASIC and FPGA technologies. His main expertise is related to ASICs and systems-on-chip in the field of networks, radio, cryptography, hardware-reconfigurable platforms, multi-cores and trusted computing. In March 2020, he joined Thales Research & Technology as an architect and a project leader in the field of RISC-V and open hardware, with special interest on embedded efficient computing, functional safety and security. Jérôme has been the chair of the Functional Safety special interest group at RISC-V International since 2020. At the OpenHW Group open-source organization, he holds the position of Technical WG, vice-chair Cores TG, technical project leader for CVA6 (a RISC-V application core).

Kexiang Yang – Ventus: an RVV-based General Purpose GPU Design and Implementation

Kexiang Yang (Tsinghua University, Beijing, China) , Hualin Wu, Jingzhou Li, Jin Chufeng, Yujie Shi, Xudong Liu, Zexia Yang, Fangfei Yu, Mingyuan Ma, Sipeng Hu, Tianwei Gong, Hu He.

Poster #24 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

Graphics Processing Units (GPUs) have become the most popular platform for accelerating modern applications such as Machine Learning, Signal Processing, and Graph workloads. Modern GPUs use Single Instruction, Multiple Thread (SIMT) structures to schedule several Single Instruction, Multiple Data (SIMD) pipelines, thus maximizing Data Level Parallelism. In this work, we propose Ventus, a General Purpose GPU (GPGPU) implementation based on the RISC-V Vector Extension (RVV). Lanes in the warps of Ventus are organized as a vector-thread architecture. We add self-defined instructions, such as branch, register index extension and Tensor Core related instructions to fulfill the functional requirements of a GPGPU. We accomplish a complete OpenCL to RVV compiler and driver that fit our hardware design. Ventus is successfully deployed on an FPGA-based platform and scales up to 16 SMs with a total of 256 warps. This work is developed in Chisel HDL and is now open-sourced on Github.

Bio

Kexiang Yang is a master’s student from the School of Integrated Circuits, Tsinghua University, where he received his Bachelor of Engineering degree in 2020. His research focuses on AI accelerator and GPGPU microarchitecture design. He is a member of Professor Hu He’s group and he has contributed to Ventus (an open-source RISC-V GPGPU)

Jose Miranda – X-HEEP: an open-source eXtendible Heterogeneous Energy-Efficient RISC-V Platform for Embedded-class systems

Jose Miranda (Openhw Group, Geneva, Switzerland) , Davide Schiavone, Simone Machetti, Miguel Peón-Quirós, Benoît Denkinger, Thomas Christoph Mueller, Rubén Rodríguez, David Atienza.

Poster #25 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

This abstract presents X-HEEP, an open-source, configurable, and extensible single-core RISC-V microcontroller targetting edge-computing, embedded-class applications.

Bio

Jose A. Miranda Calero, member IEEE, received his PhD in 2022 at the Microelectronic Design and Applications (DMA) research group, which belongs to Universidad Carlos III de Madrid. He is currently a Post-Doc Research Scientist at the Embedded System Laboratory in EPFL, Switzerland. His research field comprises wireless sensor networks, wearable design, development and integration for safety and real-time critical applications, affective computing implementation into edge computing devices, hardware acceleration, and . Regarding the development of wearable technology for safety applications, his main contribution relates to the design of BINDI, which is a new autonomous, smart, inconspicuous, connected, edge-computing-based, and wearable solution able to detect and alert when a user is under a gender violence situation employing emotion recognition using the physiological and physical signals of the user.

Quentin Schibler – You only use 10% of your FPGA

Quentin Schibler (École Normale Supérieure Paris-Saclay, Cambridge, United Kingdom)

Poster #26 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

A RISC-V processor design is usually expected to be clocked at most at 300MHz on the latest high-end FPGAs, 100MHz being a reasonable average guess. One day I opened up a data sheet and read that Intel’s Stratix 10 routing fabric can be clocked at 1GHz. This is one order of magnitude higher, but can we reach such a high frequency, and if not, what is the practical limit? As I set out to explore how fast and resource-efficient a RISC-V CPU can be on FPGAs, I will share a few guidelines I discovered along the way. Topics will include various strategies to make timing analysis doable for large designs, how to take advantage of hyper-registers, reducing area using BRAMs without sacrificing performance, and managing resets and other high-fanout signals.

Felix Garcia-Carballeira – CREATOR: a tool for teaching assembly programming with RISC-V

Felix Garcia-Carballeira (Universidad Carlos III De Madrid, Leganes, Spain) , Alejandro Calderon, Diego Camarmas-Alonso, Elias del Pozo-Puñal.

Poster #27 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

This paper introduces CREATOR, a simulator specially designed for teaching assembly programming. CREATOR allows to define different instruction sets and to edit, and execute assembly programs. This simulator includes more than 100 instructions of the RV32IMFD specification. CREATOR runs directly in web browsers without needing a server and is adapted to run on different devices (desktops, tablets, and smartphones). Unlike other simulators, it includes error detection in the parameter passing convention with alerts if the convention is violated, it helps the creation of teaching materials with the possibility of obtaining a URL that allows the execution of the simulator with a given program, and it offers capabilities to extend the instruction set with new instructions and pseudo-instructions that allows the student to experiment with further instructions.

Bio

Graduated in Computer Science at the Faculty of Computer Science of the Polytechnic University of Madrid in 1993 and Ph.D. in Computer Science from the Polytechnic University of Madrid in 1997. Currently is Professor at the Department of Computer Science and Engineering Department from the University Carlos III of Madrid. His teaching activity covers Bachelor’s and Master’s courses in Computer Architecture, Operating Systems, and Parallel and Distributed Systems. His research activity is centered on High-Performance Computing, Distributed Systems, and Systems Simulation. He has co-authored more than 140 papers in international journals and conferences. Additionally, he has participated in 36 competitive funding projects and 16 research and technology transfer contracts with companies. He has been advisor in 10 Ph.D. theses in the area of High-Performance Computing and Distributed Systems.

Alvise Rigo – VOSySzator: A flexible embedded RISC-V system virtualizer targeting the cloud

Alvise Rigo (Virtual Open Systems, Grenoble, France) , Daniel Raho, Samuele Paone, Timos Ampelikiotis.

Poster #28 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

VOSySzator [1] is a flexible embedded system virtualizer based on rust-vmm building blocks which was originally conceived by Virtual Open Systems to target embbedded virtualization use cases. It was specifically designed to overcome challenges that embedded system integrators are asked to address when implementing fast and low-overhead virtualization solution. However, as part of the Vitamin-V 2023-2025 Horizon Europe project’s action, it will be extended to support cloud use cases as well, specifically for the RISC-V architecture. The features set of VOSySzator as virtualization solution for embedded systems is of interest for the RISC-V architecture which has many similarities to existing embedded architectures like ARMv8.

Bio

Alvise Rigo (male), is a senior virtualization engineer. In July 2013, he obtained a Master degree in computer engineering from the University of Padua, discussing the development experience of a computer vision application. Since June 2013 he is member of Virtual Open Systems, joining various European projects as a virtualization expert. His professional and research activities, focused mainly on hardware emulation and virtualization, allowed him to mature an in-depth knowledge of various Open Source projects, QEMU and its internals especially, but also rust-vmm and other niche virtualization technologies. He has coordinated several contributions in FP7, H2020 and Horizon European research projects. He has led various customer projects to extend existing BSPs with ad-hoc virtualization layers and technologies to fit customers’ specific use cases in industrial, consumer and telecommunications domains. He has authored several publications and held a patent.

Stanislaw Kaushanski – Automated Cross-level Verification Flow of a Highly Configurable RISC-V Core Family with Custom Instructions

Stanislaw Kaushanski (MINRES Technologies GmbH, Munich, Germany) , Eyck Jentzsch.

Poster #29 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

As the RISC-V ISA continues to gain popularity and adoption, there is a growing need for highly configurable RISC-V cores that can be customized for specific use cases and applications. However, the complexity and variability of these cores make verification a significant challenge, especially when it comes to verifying custom instructions. In this paper, we present a cross-level [1] test environment to verify all cores with custom instructions and various interfaces without manual adjustments of the test environment, which significantly reduces the time and effort required for verification.

Lavanya Jagadeeswaran – Changing the RISC-V Verification Paradigm with Vyoma’s Verification-as-a-Service Framework

Lavanya Jagadeeswaran (Vyoma Systems Private Limited, Chennai, India)

Poster #30 in MR12-13-14 on Wed 7th. Link: extended abstract.

Summary

Design Verification has traditionally been a closed development, high-cost resource (in terms of time, manpower) usage endeavor. In order to keep up with the growing trend of the increasing complexity of designs and its open standard methodologies, Vyoma’s Verification-as-a-Service technology targets improved verification productivity leveraging state-of-the-art verification frameworks (Python-based) and compute infrastructure (Cloud-based). This provides a practical shift-left methodology for next-generation verification needs without compromising on the design verification quality.

Muhammad HASSAN – Expanding RISC-V Horizons: Streamlining Heterogeneous Systems Evaluation with Open Source RISC-V AMS VP Framework

Muhammad HASSAN (DFKI GmbH And University Of Bremen, Bremen, Germany) , Rolf Drechsler, Sallar Ahmadi-Pour.

Poster #31 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

In this extended abstract, we present the RISC-V AMS VP framework, an evaluation platform that combines the open source RISC-V Virtual Prototype (VP) with SystemC AMS (Analog/Mixed Signal) for accurate environment modeling of heterogeneous systems. The RISC-V Instruction Set Architecture (ISA), with its modular and extensible design, has garnered significant popularity in academia and industry. The growing RISC-V ecosystem includes various tools, simulators, and processor implementations for supporting the development flow. However, the integration of SystemC AMS with RISC-V VPs has not been explored thus far. The proposed RISC-V AMS VP framework provides a unified view of software, hardware, and AMS environment models, enabling design and verification engineers to accurately interact with the system at different levels and perform powerful analyses. As a case study, we created a temperature control system that integrates a sensor, heater component, and control software running on a RISC-V platform. We also briefly discuss a fault- injection evaluation, considering different modeling layers. We provide the RISC-V AMS VP framework and the temperature control system case study as open source resources, laying the foundation for further research and education in this field.

Bio

Mr. Hassan did his PhD in computer science from University of Bremen under the supervision of Prof. Rolf Drechsler. He did his MSc From RWTH Aachen in communication engineering. He is currently a senior researcher at DFKI and a Post-doc at University of Bremen. His research interests include RISC-V design and verification, mixed-signal verification at system level, compiler construction, and blockchain.

Tanuj Khandelwal – Functional Verification Strategy for an Open-Source High-Performance L1 Data-Cache for RISC-V cores

Tanuj Khandelwal (Univ. Grenoble Alpes, CEA, LIST, Grenoble, France) , Ludovic Pion, César Fuguet Tortolero, Adrian Evans.

Poster #32 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

The verification of caches is particularly challenging, as it is necessary to ensure that the memory consistency is ensured in all conditions and modern caches contain many complex features (out of order execution, write buffer, multiple request ports) and a complex micro-architecture in order to ensure high-performance. The recently released, Open-Source High Performance L1 Data Cache (HPDCache) for the RISC-V is delivered as a highly configurable RTL model, compounding the verification challenge as correct behaviour must be ensured for all combinations of the parameters. An approach combining pseudo random constraint and directed random test within the framework of Universal Verification Methodology (UVM) is used to be able to verify HPDcache.

Alberto Moreno – RISC-V Core FPGA tracing for verification

Alberto Moreno (Semidynamics, Barcelona, España) , Jordi Cortina, Alex Torregrosa, Roger Espasa.

Poster #33 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

This paper introduces an FPGA verification, debug and performance platform for RISC-V cores. The system utilizes the open source RISC-V simulator Spike as a golden model that can be co-emulated with the core in real time. In our experience, this enables verification at up to 50 MHz. This allows for rapid iteration of new features by testing them in a realistic environment without a previous need for unit-level verification. The platform may also be configured to act unobtrusively in order to generate real time accurate performance metrics.

Bio

Alberto Moreno obtained his PhD in Computer Science from Universitat Politècnica de Catalunya in 2019. He has since been working as a Digital Design Engineer at Semidynamics, helping develop the RISC-V core families Avispado and Atrevido. His current position is Tech Lead for the Atrevido pipeline.

Fatima Saleem – Open-Source RISC-V Vector Test Suites: A Comparative Analysis

Fatima Saleem (10xengineers, Lahore, Pakistan) , UMER IMRAN, Quswar Abid, Kamran Malik.

Poster #34 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

Architecture-level verification of RISC-V Vector (RVV) cores presents a complex challenge due to the diverse behavior of vector instructions under various instruction parameters and core configurations. The vector instruction test suite must be capable of addressing all legitimate combinations of vector instructions under all the different configurations to accomplish comprehensive verification targets. In this paper, we present a comparative analysis of seven open-source test suites for vector ISA: Imperas, RIOS Labs, RISCV-Torture, RISCV-DV, FORCE-RISCV, Yang’s Generator and Tenstorrent. We provide an objective evaluation of the attributes and coverage of these test suites using the RVV Specification v1.0 as a reference. Our study reveals that a combination of these test generators can provide a fairly comprehensive verification strategy for vector cores. On a stand alone basis, FORCE-RISCV covers the complete RVV v1.0 specification upto a VLEN of 4096. Similarly, Imperas is fairly exhaustive but limited to VLEN of 256.

Bio

Fatima is a Senior Engineer at 10xEngineers, a company dedicated to developing leaders in RISC-V design verification in Pakistan. With a focus on the design and verification of a RISC-V Vector processor mainly the load store unit, she has extensive experience in the coverage closure of various SiFive cores and feature verification of a Coherent Manager Cache, including MSHRs, Loosely Integrated Memory, and Performance Monitor. In her pursuit of expertise in Core and SoC Design Verification, Fatima remains committed to contributing to the open-source community and is an active contributor to the OpenHW CVA6 core. She is driven to excel in this field and seeks opportunities to collaborate and enhance her skills.

Peter Rugg – Randomized Testing of RISC-V CPUs using Direct Instruction Injection

Peter Rugg (University Of Cambridge, Cambridge, United Kingdom) , Alexandre Joannou, Jonathan Woodruff, Franz Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter Neumann, Simon W. Moore.

Poster #35 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

We present TestRIG, a test framework for RISC-V implementations. To use TestRIG, a Direct Instruction Injection interface is added to the implementation under test. Direct Instruction Injection allows the test framework to inject instructions directly into the processor’s pipeline (instead of instructions being fetched from program memory). The Direct Instruction Injection approach simplifies randomized testing, particularly when the test programs contain branch instructions. We describe some of the main challenges in randomized testing of CPUs, and explain how TestRIG overcomes them. Finally, we give examples of some hardware bugs that were found using TestRIG, including bugs in the floating point library supplied with the BlueSpec compiler and bugs that were detected during development of the CHERI security extension.

Bio

Peter Rugg is a PhD student at the University of Cambridge Department of Computer Science and Technology in England specialising in efficient capabili

Josep Sans I Prats – Open source verification environment for RISC-V

Josep Sans I Prats (Semidynamics, Barcelona, España) , Alberto Moreno, Alex Torregrosa, Roger Espasa.

Poster #36 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

Open source verification environment for RISC-V

Bio

Josep got his Masters degree on High Performance Computing by the UPC and he has been working in the Semidynamics verification team focusing on the Load Store pipeline of the cores.

Marno van der Maas – Verifying Enhanced PMP Behavior in Ibex

Marno van der Maas (lowRISC CIC, Cambridge, United Kingdom) , Andreas Kurth, Harry Callahan, Gregory Chadwick.

Poster #37 in MR12-13-14 on Wed 7th. Link: poster.

Summary

To uphold the principle of least privilege, RISC-V can further limit M mode’s access to memory through PMP enhancements in the Smepmp extension. Ibex is an open-source processor, and it uses these enchancements to be a compelling choice for security-critical applications. Because Ibex is thoroughly verified and production quality, the verification requirements are high for adding this extension. In this proposal, we design a coverage plan for Smepmp, generate sensible constrained-random Smepmp configurations and add directed tests to maximize coverage of corner cases. Smepmp poses a particular challenge because many transitions and configurations lead to immediate faults, such as when MML is enabled and the PC is not in an executable region. Through this work, we improve the overall PMP coverage with Smepmp from 63 % to 98 %.

Bio

Dr Marno van der Maas completed a PhD at the University of Cambridge in 2022 on protecting trusted execution environments from side-channel attacks. During this time, Dr Van der Maas also worked on implementing and testing processors that enforce bounds and permissions on memory pointers using a technology named Capability Enhanced RISC Instructions (CHERI). At lowRISC CIC, Dr Van der Maas works on open silicon, primarily on the OpenTitan and Ibex projects. His previous experience on verification and security enables him to contribute to the vision of making open silicon a reality.

Yassine Eben Aimine – Wedging with formal verification to strengthen the quality of custom RISC-V SoC

Yassine Eben Aimine (Siemens EDA) , Nicolae Tusinschi, Salaheddin Hetalani, Pascal Gouedo.

Poster #38 in MR12-13-14 on Wed 7th.

Summary

On the path of creating high-quality processor IP a major challenge is the need to verify the correctness of the design across a wide range of configurations and use cases. Each configuration needs to be validated and can be challenging to ensure all possible input patterns are exercised and functions are correctly implemented. In this paper, we go through a novel approach in verifying an open-source, high-quality and customizable RISC-V core with a comprehensive methodology. We explain the importance of thorough planning, use of automated code review and exhaustive formal guided automation. We provide evidence illustrating how proposed methodology is cost-effective and highly efficient in preventing bugs to escape and accelerates sign-off process.

Bio

Over 20 years’ experience in EDA software pre-sales and after-sales in the semiconductor industry. From technical account management, technical marketing, lead generation to hands-on product evaluations and successful customer deployment.

Jon Taylor – Adapting verification methodologies and techniques for the innovation of RISC-V

Jon Taylor (Imperas Software) , Aimee Sutton, Lee Moore, Simon Davidmann.

Poster #39 in MR12-13-14 on Wed 7th.

Gregory Chadwick – Building commercially relevant open source silicon: The many aspects of Ibex

Gregory Chadwick (Lowrisc Cic, Bristol, United Kingdom) , Andreas Kurth, Marno van der Maas, Harry Callahan.

Poster #40 in MR12-13-14 on Wed 7th. Link: extended abstract.

Summary

Ibex [1] is an open source RV32IMCB CPU with a 2 or 3 stage pipeline (configurable at synthesis) targeting embedded and security applications. It started life as zero-riscy [2] from ETH Zürich who contributed it to lowRISC [3], and its development is now part of the OpenTitan [4] project. lowRISC’s aim with Ibex (as with all of the IP it maintains) is not only to make high quality RTL freely available under a permissive licence, but to ensure it meets the needs of commercial users with the goal of enabling wide-scale adoption of open source silicon designs. To achieve this, it is not enough to simply make the RTL available. The code needs to meet high quality standards, be in a form that is usable and familiar for industry, and to be credible. A core part of credibility is achieving full verification up to the standard required for commercial tape outs. Crucially the verification framework itself as well as test and coverage plans are fully open source so they can be properly scrutinised. Regular regression results are published to demonstrate IP maturity and underscore our long-term commitment to it. In this proposal we present the collaborative engineering lowRISC and the community have done on Ibex. There is an overview of the design and configuration options; details of the full UVM based testbench, test suite and coverage plan; and a discussion on lowRISC’s quality standards.

Bio

Greg is the digital design lead at lowRISC, where he develops Ibex and works on the OpenTitan Project (an open silicon root of trust). His work at lowRISC includes SoC architecture, CPU design, security hardening and verification. He has close to 10 years experience in the silicon industry, having worked on the design of memory systems for A class CPUs at Arm and GPU design at Broadcom. He completed his Ph.D at the Cambridge Computer Laboratory (UK) in 2011 with the thesis ‘Communication centric, multi-core, fine-grained processor architecture’

Gert Goossens – Taking the Risk out of Optimizing Your Own RISC-V Architecture Design

Gert Goossens (Synopsys, Leuven, Belgium) , Patrick Verbist, Dominik Auras.

Poster #42 in MR12-13-14 on Wed 7th. Links: extended abstract, poster.

Summary

An important driver behind the growth of RISC-V is the ability to customize or create ISA and microarchitectural extensions to differentiate designs across application areas. This results in application-specific processors (ASIPs) composed of a RISC-V baseline architecture, extended with specialized datapaths and storage structures. Designing such extended processors can be challenging. First, deciding which extensions are best for the target application domain is not obvious. Second, software developers expect to get access to a high-quality software development kit (SDK) for the application-specific processor. Third, a reliable and efficient register-transfer level (RTL) implementation of the processor must become available for silicon implementation. This presentation will show how electronic design automation (EDA) tools can solve these challenges. ASIP Designer is Synopsys’ leading tool for the design of custom processors. It has been applied successfully by customers worldwide to design extended RISC-V processors for a multitude of application domains.

Bio

Gert Goossens is a Senior Director of Engineering at Synopsys, where he is currently leading the company’s tool development group for Application-Specific Instruction-set Processors (ASIPs). Previously, he was a co-founder and the CEO of Target Compiler Technologies, the company that pioneered the concept of ASIP tools. Gert Goossens holds MS and Ph.D. degrees from KU Leuven, Belgium.

Posters on Display Thursday June 8th

Presenters are expected to be with their poster during the morning break, lunch and afternoon break.

Michael Wong – Towards RISC-V Datacenter and Cloud Computing with Accelerators, Ecosystem and new ISA

Michael Wong (Codeplay, Toronto, Canada)

Poster #1 in MR07-08 on Thu 8th.

Hualin Wu – Accelerate HPC and AI applications with RVV auto vectorization

Hualin Wu (Terapines Ltd, Wuhan, China) , Ming Yan.

Poster #2 in MR07-08 on Thu 8th. Links: extended abstract, poster.

Summary

RISC-V is an open and free ISA designed to be modular. It enables new business models. Increasingly, AI chips and other DSAs are adopting RISC-V. With the finalization of the RISC-V Vector extension, the industry is looking for innovative solutions to accelerate AI and HPC applications. Maintaining a wide range of hand-optimized intrinsic kernels for various AI chips is costly and difficult to scale. We believe that RVV auto-vectorization is the key technique to alleviate this burden on human resources. We have evaluated the auto-vectorization performance of our LLVM-based compiler ZCC on some popular kernels, and it shows that ZCC has an 18% better dynamic instruction count performance compared to hand-optimized kernels written in RVV built-in functions. To the best of our knowledge, ZCC is the only one that can successfully auto-vectorize both inner and outer loops by fully utilizing RVV features. ZCC has also achieved a 30% better performance (dynamic instruction count) compared to LLVM on SPECInt 2006.

Bio

Hualin Wu is the co-founder and CTO of Terapines Technology. He was worked in Andes, S3 and Imagination as CPU/GPU compiler/driver engineer for almost 10 years before starting Terapines. Terapines is mainly focus on developing RISC-V co-design software including ZCC compiler (based on LLVM), ZVC compiler (based on MLIR/CIRCT), virtual prototyping tool ZEMU (highly reconfigurable ISA and cycle accurate simulator), ZProf (function level to microarchitecture level performance analyzer), cloud/desktop IDE ZStudio and DSP libraries etc.

Philipp van Kempen – Automated Generation of a RISC-V LLVM Toolchain for Custom MACs

Philipp van Kempen (Technical University of Munich, Munich, Germany) , Karsten Emrich, Daniel Mueller-gritschneder, Ulf Schlichtmann.

Poster #3 in MR07-08 on Thu 8th. Links: extended abstract, poster.

Summary

RISC-V is an instruction set architecture (ISA) that, as a core feature, can be extended with special instructions to customize embedded processors to special applications such as from the control and machine learning domain. There exist several instruction set simulators (ISS), that can quickly evaluate the benefit of special instructions for a given application. Next to the core, also the compiler and assembler support for creating a binary from embedded C code is required by designers to exploit performance benefits of special instructions such as Multiply and Accumulate (MAC) operations. We introduce a code generation tool for extending existing LLVM implementations with support for custom RISC-V instructions described in the CoreDSL format.

Bio

Working in Electronic System Level (ESL) group of the EDA chair developing solutions for deployment challenges related to Extreme Edge AI applications (TinyML), mainly for RISC-V targets. This includes optimizations at several stages of the design process (Training, Hardware Design and SW Deployment) e.g. by using Network Architecture Search (NAS), improving existing machine learning tools and proposing ISA extensions in a highly automated fashion.

Léo Gourdin – Formally verified advanced optimizations for RISC-V

Léo Gourdin (UGA, Grenoble, France) , Léo Gourdin, Sylvain Boulmé.

Poster #4 in MR07-08 on Thu 8th. Link: poster.

Summary

We implemented and formally proved code hoisting, loop-invariant code motion (LICM) and strength reduction for RISC-V by translation validation. This approach consists in splitting the pass into an unproved transformation—called an “oracle”—and a formally proved defensive verifier. More specifically, our verifier is based on symbolic execution; a well-known general purpose validation technique that simulates the possible execution paths of the code using a symbolic representation of registers and memory. Our transformations improve on those proposed by Knoop et al. The oracle is co-designed with the verifier and logs information, such as invariants, that help the verifier check equivalence; whereas other attempts at translation validation had to reconstruct these invariants heuristically.

Bio

I am a third year PhD student in Grenoble, France. My main research interests are: formal proof, compilation, processors architecture / instruction sets, optimization, and code safety & security. During the last three years, I worked on the formal verification of optimizations, and in particular for the CompCert certified compiler on the RISC-V backend. My thesis focus on formal verification of translation validators: I study how symbolic execution can help in validating the results of optimizations algorithms. In the future, I may study how this approach can be reused to also ensure semantics preservation while securing the code with counter-measures. In other words, how a unique formally verified validation technique can help for both safety and security concerns. Before starting this PhD, I did an engineering school and worked in a company conceiving embedded RFID chips (ASYGN).

Henri-Pierre Charles – How to generate data dependent applications and handle platform heterogeneity ?

Henri-Pierre Charles (CEA, Grenoble, France) , Maha Kooli, Thaddée Bricout, Benjamin Lacour.

Poster #5 in MR07-08 on Thu 8th. Links: extended abstract, poster.

Summary

Modern applications are dynamic. There are many dynamicity aspects : dynamic allocation, user chosen data sets, user chosen parameters, dynamic / interpreted languages, indirect memory access, transprecision . . . RISCV-V modern processors contains also dynamic behaviour : data and instruction caches, pipelines . . . Aggressive compilers are unable to catch so many dynamic application aspects, but there is a need to adapt binary code to those two dynamic aspects because run-time behaviour contains huge optimization opportunities. RISCV-V has also a specific difficulty : since the ISA is open, there is many implementations with subtle variants : specifics accelerators, special instructions, special register banks. Those variants are difficult to handle with a monolitic compiler. HybroGen is an experimental compiler designed to build application with dynamic binary code adaptations.

Bio

Dr Henri-Pierre Charles is research director in CEA-LIST since September 2010. His educationnal background is a master degree in computer science in 1987 and a PhD in 1993 from INPG, Grenoble, France. He was university lecturer in Versailles University during 17 years since 1993. Since his CEA arrival he has participated in many collaboratie projects, mainly in the HPC domain. He has supervised many PHD thesis on code optimizations and High performance computing. His research interests are in dynamic compilation, Low level code optimization and new methods for code generation for high performances and multimedia applications. He has developed the concept of « compilettes » that can be defined as tiny compilers embedded into applications, able to generate optimal code depending on the data characteristics. The “compilettes” was generated by the former deGoal compiler and, since 2022, with the open source compiler HybroGen.

Zdenek Prikryl – RISC-V as an Enabler of Heterogeneous Compute

Zdenek Prikryl (Codasip)

Poster #6 in MR07-08 on Thu 8th. Link: poster.

Summary

With the end of the well-established scaling, and laws, such as Dennard scaling, Amdahl’s law, or even Moore’s law, thw wider industry has started looking at possible solutions. One of the solutions that has emerged is heterogeneous compute. In its essence it solves the problem by having individual computational blocks, i.e., processors, that are specialized/customized for a certain job or workloads. Although this idea is not new and we can see an evidence of it in the past, the design of such processors has been challenging and requires not only deep technology knowledge, but also a significant amount of resources and time. In this paper, we present a novel approach to heterogeneous compute that is based on pre-verified processors that designers can further innovate using supplied EDA tools. The pre-verified processors and their control and data paths are prepared for the heterogeneous compute and therefore the knowledge and resource requirements are reduced to a minimum. The designers focus on what really matters to them instead of reinventing the wheel for the baseline of the processor or its instruction set.

Henri-Pierre Charles – RISC-V based Programming Model of a Computational SRAM Vector Processing Unit

Henri-Pierre Charles (Cea Grenoble, Grenoble, France) , Jean Philippe Noël, Bastien Giraud, Thaddée Bricout, Maria Ramirez Corrales.

Poster #7 in MR07-08 on Thu 8th. Links: extended abstract, poster.

Summary

Computational SRAM (C-SRAM) is a new computing solution for Near-Memory Computing. It allows to perform operations inside or next to the memory without transferring data over the system bus, leading to significantly reducing energy consuption. Operations are realized on large vectors of data occupying the entire physical row of C-SRAM array, leading to high performance gains. This paper presents the C-SRAM solution as an integrated vector-processing unit to be used by a RISC-V processor as an energy-efficient and high performing co-processor. The proposed programming model of the C-SRAM is based on the system bus of a RISC-V processor.

Bio

Dr Henri-Pierre Charles is research director in CEA-LIST since September 2010. His educationnal background is a master degree in computer science in 1987 and a PhD in 1993 from INPG, Grenoble, France. He was university lecturer in Versailles University during 17 years since 1993. Since his CEA arrival he has participated in many collaboratie projects, mainly in the HPC domain. He has supervised many PHD thesis on code optimizations and High performance computing. His research interests are in dynamic compilation, Low level code optimization and new methods for code generation for high performances and multimedia applications. He has developed the concept of « compilettes » that can be defined as tiny compilers embedded into applications, able to generate optimal code depending on the data characteristics. The “compilettes” was generated by the former deGoal compiler and, since 2022, with the open source compiler HybroGen.

Jack Andrew – Virtual machines on RISC-V

Jack Andrew (Imagination Technologies, Cambridge, United Kingdom)

Poster #8 in MR07-08 on Thu 8th. Link: extended abstract.

Summary

This extended abstract is submitted as a poster submission for the RISC-V Summit Europe, Barcelona, 5th-9th June 2023. It is assumed that the reader has a basic understanding of RISC-V and computer architecture. The poster aims to be a primer into virtual machines on RISC-V from a hardware/software co-design perspective. It introduces virtual machines and the associated software concepts. The poster closes by analysing two virtual machine topics that are critical to the commercial success of RISC-V and how they might be addressed in hardware and software.

Bio

I’m Jack, Senior Principal Engineer at Imagination Technologies working on developing their RISC-V CPUs. Initially, Ied RTXM-2200, a performance dense 32-bit CPU, to it’s first release to customers. I’m now focusing on a next generation applications class CPU. Previously, I spent 8 years working on M-class CPU development at Arm. Initially, I worked on Cortex-M7, a high-performance DSP focused CPU, to close verification. Following this, I defined the debug uArchitecture and heavily contributed to the entirety of Cortex-M33, a highly energy efficient CPU with a security focus. At this stage, I accelerated my career by taking a leadership role on Cortex-M55 by leading the design of the first ever M-class Vector Extensions datapath. These three CPUs targeted a range of markets including Embedded, IoT, Auto, AI, and Mobile.

Martin Troiber – A Vulkan Graphics Driver for RISC-V CPUs

Martin Troiber (Technical University Of Munich, Munich, Germany)

Poster #9 in MR07-08 on Thu 8th. Links: extended abstract, poster.

Summary

This report presents the first open-source Vulkan graphics driver for RISC-V. We achieved this by porting SwiftShader - a graphics driver targeting CPUs - to RISC-V. For the evaluation of our port we utilized QEMU emulation and the Allwinner D1 RISC-V chip. On RISC-V chips without a GPU this is the first time rendering 3D graphics with Vulkan is possible. This is particularly important for server CPUs or low cost RISC-V chips which are often used on single board computers.

Bio

Martin Troiber is a Masters student in Informatics at the Technical University of Munich. His areas of interest are Computer Architecture and Software Engineering with a particular focus on GPUs and graphical applications. During his studies he has made open-source contributions to the BlackParrot RISC-V core, the LiteX SoC builder and the Swiftshader Vulkan driver. The work presented was part of a university project in winter of 2021/2022. The overall goal of the project was to explore possible future GPU architectures based on RISC-V cores.

Iacopo Colonnelli – Experimenting with PyTorch on RISC-V

Iacopo Colonnelli (University Of Torino, Torino, Italy) , Robert Birke, Marco Aldinucci.

Poster #10 in MR07-08 on Thu 8th. Link: extended abstract.

Summary

RISC-V is an emerging instruction set architecture. Its modular and extensible open-source royalty-free design is increasingly attracting interest from both research and industry. Nowadays, different RISC-V-based boards can be bought off the shelf. However, software availability is equivalently vital in guaranteeing the RISC-V ecosystem’s success. Here we contribute with the first publicly available port of PyTorch. PyTorch is one of the most popular Deep Learning libraries available today. As such, it is a crucial enabler in running state-of-the-art AI applications on RISC-V-based systems and a first step towards a fully democratic end-to-end codesign process.

Bio

Iacopo Colonnelli is a Computer Science assistant professor (RTDA). He received his Ph.D. with honours in Modeling and Data Science at Università di Torino with a thesis on novel workflow models for heterogeneous distributed systems, and his master’s degree in Computer Engineering from Politecnico di Torino with a thesis on a high-performance parallel tracking algorithm for the ALICE experiment at CERN. His research focuses on both statistical and computational aspects of data analysis at large scale and on workflow modeling and management in heterogeneous distributed architectures. He is a member of the CWL Technical Team.

Jonas Hahnfeld – Porting ROOT and Cling to RISC-V

Jonas Hahnfeld (CERN, Geneva, Switzerland)

Poster #11 in MR05-06 on Thu 8th. Links: extended abstract, poster.

Summary

The ROOT data analysis framework is used to analyze exabytes of data in the domain of High Energy Physics (HEP). One critical ingredient is its interactive C++ interpreter Cling, powering many areas of ROOT from the IO layer to interoperability with Python. Outside of HEP, Cling is also used to provide the C++ kernel for Jupyter notebooks. The interpreter is built on top of LLVM and Clang and uses just-in-time compilation (JIT) to emit and execute native machine code. In this contribution, we describe the work required to port ROOT and Cling to the RISC-V architecture. We describe the changes needed to run a first physics analysis and put special emphasis on the particularities for supporting RISC-V’s modular ISA design.

Bio

Jonas graduated with a M.Sc. in Computer Science from RWTH Aachen University and joined CERN as a Junior Fellow in November 2020. In the EP-SFT group, he works on the detector simulation framework Geant4 and the R&D project AdePT that prototypes electromagnetic shower simulation on GPUs. He is also part of the ROOT team where he focuses on the Cling interpreter and performance related improvements to various parts of the framework. While there is an overlap with his work topics, the present contribution has been carried out in his free time, in the context of the RISC-V Developer Board program.

Hugo McNally – Relocatable RISC-V Rust Applications for Embedded Systems

Hugo McNally (Lowrisc Cic, Cambridge, United Kingdom) , Luís Marques, Jorge Prendes.

Poster #12 in MR05-06 on Thu 8th. Links: extended abstract, poster.

Summary

The embedded position independent code (ePIC) ABI proposal offers a solution to the challenge of generating relocatable applications for RISC-V embedded systems without an MMU. Having such an ABI is important for enabling the dynamic loading of relocatable applications in the embedded RISC-V ecosystem. This unlocks the full potential of secure platforms such as Tock, an operating system that builds on the Rust compiler guarantees to help minimize the security vulnerabilities in embedded systems. This extended abstract outlines the unique features of ePIC, particularly in comparison to the approaches used in non-embedded devices, and highlights its significance for a secure Rust platform in embedded systems.

Bio

Hugo McNally is a Hardware/Software Engineer at lowRISC CIC. He is passionate about helping build high quality open silicon designs. Currently, his main areas of focus are top level verification of the OpenTitan platform and further improving the documentation of the platform.

Jérôme Fereyre – VPSDK : a portability library for extended arithmetic operations targetting a RISC-V Variable eXended Precision accelerator.

Jérôme Fereyre (Cea, Grenoble, France) , Alexandre Hoffmann.

Poster #13 in MR05-06 on Thu 8th. Links: extended abstract, poster.

Summary

We develop a RISC-V based accelerator called VXP (Variable eXtended Precision). It provides an efficient way to handle extended precision arithmetic operations. This helps to address convergence issues encountered using linear algebras solvers for scientific applications. In the current work we introduce a library called VPSDK. VPSDK is a general framework to develop application on this accelerated environment as well as in general purpose architectures.

Arthur Perais – We had 64-bit, yes. What about second 64-bit?

Arthur Perais (CNRS, Grenoble, France) , Mathieu Bacou, Adam Chader, Chandana Deshpande, Christian Fabre, César Fuguet Tortolero, Pierre Michaud, Frédéric Pétrot, Gaël Thomas, Eduardo Tomasi Ribeiro.

Poster #14 in MR05-06 on Thu 8th. Links: extended abstract, poster.

Summary

High-performance architectures are increasingly heterogeneous and incorporate often specialized hardware. We have first seen the generalization of GPUs in the most powerful machines, followed by FPGAs, and now by many other accelerators such as Tensor Processor Units (TPUs) for Deep Neural Networks, or variable precision FPUs. Recent hardware manufacturing trends make it very likely that specialization will not only persist, but increase. Manually managing this heterogeneity is complex and not maintainable. We therefore propose to revisit how we design both hardware and OS in order to better hide the heterogeneity. To ensure long term viability of our proposal, we propose to entertain the use of 128-bit addressing.

Bio

Arthur Perais is a full-time researcher at TIMA (Grenoble, France), focusing on general purpose high performance processor microarchitecture. He obtained his Ph.D. in 2015 from Inria at University of Rennes, and was previously a hardware engineer with Qualcomm and Microsoft until 2020.

Andrei Warkentin – Multi-ISA Firmware Compatibility – Bringing RISC-V and IHV Ecosystems Together

Andrei Warkentin (Intel Corporation, South Elgin, United States)

Poster #15 in MR05-06 on Thu 8th. Link: extended abstract.

Summary

There are a number of challenges to a successful standards-based RISC-V ecosystem that enables PC and server-like designs. One important challenge is interoperability with the existing IHV device ecosystem. How can we bring familiar off-the-shelf PCIe devices, such as graphics, network, and storage adapters, to UEFI RISC-V systems with the same pre-boot experience seen on Intel 64 and SystemReady AArch64 platforms? This paper covers an emulation-based approach and presents MultiArchUefiPkg – an open-source solution.

Bio

I am a Senior Principal Engineer at Intel Corporation, where I focus on RISC-V platform standards and systems software enablement. I have 17 years of industry experience as an OS generalist, primarily focused on operating system kernels, virtualization, porting/platform bring-up and firmware. I have spent 10 years in the 64-bit Arm ecosystem wearing the proprietary OS vendor hat as an architect for Arm SmartNIC-based Project Monterey and as the Arm Enablement Architect for the VMware ESXi hypervisor, contributing to the Arm standards-first interoperable ecosystem. I was one of the primary instigators for SystemReady ES (ACPI beyond servers) specifications and the subsequent reformatting of the Arm ServerReady specification brand into Arm SystemReady. The last few years I have in various capacities worked on RISC-V, again mostly with a focus on standards, interoperability, systems-level engineering/porting and firmware.

Paul Scheffler – Accelerating Irregular Workloads with Cooperating Indexed Stream Registers

Paul Scheffler (ETH Zurich, Zürich, Switzerland) , Luca Benini.

Poster #16 in MR05-06 on Thu 8th. Links: extended abstract, poster.

Summary

Sparse and irregular workloads are crucial to various data-driven applications including computational physics, graph analytics, and sparse neural networks. However, their high control overhead and irregular memory access patterns are inefficiently handled by today’s architectures, resulting in low functional unit utilization and low overall efficiency. While proposed hardware solutions accelerate irregular workloads, most are held back by a lack of generality or their large architectural impact. We present Cooperating Indexed Stream Registers, a lightweight RISC-V ISA extension building on stream registers to accelerate three key operational patterns on index streams underlying many irregular workloads: indirection, intersection, and union. Handling these in hardware can accelerate one- and two-sided sparse linear algebra, stencil workloads, sparse neural networks, and quantized data streaming among others. In an existing eight-core RISC-V compute cluster, our extensions incur only 1.8% in additional area over affine stream registers, but accelerate sparse-dense linear algebra, sparse-sparse linear algebra, and stencil codes by up to 5.0x, 5.9x, and 3.7x, respectively while consuming up to 3.0x less energy.

Bio

Paul Scheffler received his BSc and MSc degree in electrical engineering and information technology from ETH Zurich in 2018 and 2020, respectively. He is currently pursuing a PhD in the Digital Circuits and Systems group of Prof. Benini. His research interests include hardware acceleration of sparse and irregular workloads, on-chip interconnects, manycore architectures, and high-performance computing.

Alexandre Joannou – CHERI-RISCV Extension Progress

Alexandre Joannou (University of Cambridge, Cambridge, United Kingdom) , Robert N. M. Watson, Alex Ridchardson, Jessica Clarke, John Davis, Lawrence Esswood, Ben Laurie, Simon W. Moore, Peter Rugg, Peter Sewell.

Poster #17 in MR05-06 on Thu 8th. Link: extended abstract.

Summary

The CHERI ISA extensions for security have been under development for the last 13 years and have seen implementations in the MIPS, RISCV and ARM ISAs. It has recently seen its first commercial RISCV implementation and several companies are showing interest in the technology. The CHERI-RISCV SIG aims to capture a minimum useful specification for CHERI-enhanced RV32 and RV64 ISAs. We aim to support the commercial implementation of a CHERI-enabled single-core RV32 or multicore RV64 configuration. For 64-bit, the ISA would support virtual memory suitable to use in lower-end computing environments that run operating systems such as Linux, FreeBSD, and seL4. However, our current focus is on vertically integrated hardware-software 32-bit stacks built by early adopters to provide a consistent minimal baseline that future specifications can extend.

Bio

Alexandre Joannou received a PhD in Computer Architecture from the University of Cambridge in 2018. He is currently a senior research associate at the University of Cambridge. His research interests include Computer Architecture as well as abstractions and tooling for hardware design.

Alexey Shchekin – Compact CORDIC accelerator implementation for embedded RISC-V core

Alexey Shchekin (Codasip) , Ettore Antonino Giliberti.

Poster #18 in MR05-06 on Thu 8th. Links: extended abstract, poster.

Summary

Trigonometric functions are used in many embedded systems applications, such as signal and image processing, control theory, communication systems and robotics. Taking the advantage of RISC-V ISA flexibility and Codasip processor design technologies, we propose a fast and ef icient implementation of the CORDIC algorithm implemented as custom instruction in an embedded RV32IMCB core in order to smoothly compute trigonometric functions. This customization improves the performance reducing the processing time by 24x, energy consumption by 13.5x at the cost of an additional 4% of silicon area. The CORDIC accelerator was implemented with 210 lines of CodAL code. Such a compact implementation alongside an automatically generated toolchain significantly shortening the time to ASIP market facilitating IP core customizations.

Pascal Gouédo – CV32E40P updates: customizing an open-source RISC-V core at industrial-grade; experiences and challenges

Pascal Gouédo (Dolphin Design, Grenoble, France) , Yoann PRUVOST, Xavier AUBERT, Olivier MONTFORT, Mike Thompson, Davide Schiavone.

Poster #19 in MR05-06 on Thu 8th. Links: extended abstract, poster.

Summary

This paper will focus on the design and verification strategy of an open-source RISC-V CPU for edge-computing platforms at industrial-grade.

Bio

Pascal Gouedo is the Panther multicore platform architect in Dolphin Design Processing team. He has been key in the decision of choosing CV32E40P for multicore platform core as well as using Formal Verification for RISC-V standard and custom extensions. He joined Dolphin Design in 2020 and worked before in a leading edge company where he designed general purpose and customized Cores together with their full sub-system and actively participated to Verification strategy of all those soft IPs. He started to have interest in RISC-V back in 2018, implemented and verified one small RV32IMC RISC-V core and is now leading CV32E40Pv2 CORE-V project inside OpenHW group.

Stephan Nolting – Developing Custom RISC-V ISA Extensions for General Embedded Image Processing Operations

Stephan Nolting (Fraunhofer IMS, Duisburg, Germany) , Alexander Utz.

Poster #20 in MR05-06 on Thu 8th. Links: extended abstract, poster.

Summary

Processing data-intense tasks right inside an image sensor system allows to offload real-time constraints from centralized data processing nodes and also to reduce transmission bandwidth requirements. High-performant application-tailored processors emblematize one feasible concept to cope with these demands while still providing flexibility for future revisions of the actual algorithms. This work presents an area-optimized customized RISC-V processing system designed as application-specific instruction set processor (ASIP), which is optimized to accelerate exemplary image processing operations. The proposed ISA extensions exploit single-instruction multiple-data (SIMD) concepts on pixel level, resulting in a speedup of 13 (compared to a software-only approach) while increasing the prototype’s FPGA hardware utilization by just 15%.

Daniel Vázquez – Extending RISC-V Datapaths with Coarse-Grained Reconfigurable Architectures

Daniel Vázquez (Universidad Politécnica De Madrid, Madrid, Spain) , Andrés Otero, Alfonso Rodríguez, Eduardo de la Torre.

Poster #21 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

This work proposes extending the datapath of a RISC-V processor with a CGRA, a reconfigurable general-purpose accelerator for computing a wide range of applications with higher energy efficiency and lower execution times, through custom ISA extensions. This accelerator supports the execution of computing-intensive code sections, providing the RISC-V processor with spatially-distributed computing capabilities. The proposed system has been implemented and evaluated on an FPGA device, where experimental results show up to a 13× increase in execution performance for a synthetic benchmark.

Bio

Daniel Vázquez received the B.Sc. degree in industrial electronics and automatics from the Universidade de Vigo in 2020 and the M.Sc. degree in industrial electronics from the Universidad Politécnica de Madrid (UPM) in 2021, where he is currently pursuing the Ph.D. degree in industrial electronics with the Centro de Electrónica Industrial. He was a Visiting Researcher with the Embedded Systems Laboratory, EPFL, where he worked on reconfigurable computing in a low-power RISC-V platform. His current research interests include RISC-V, hardware accelerators for embedded systems, and reconfigurable computing.

Enric Morancho – Hypervisor Extension for a RISC-V Processor

Enric Morancho , Jaume Gauchola, Juanjo Costa, Ramon Canal, Xavier Carril, Max Doblas, Beatriz Otero, Manuel Alejandro Pajuelo, Eva Rodríguez, Javier Salamero, Javier Verdú.

Poster #22 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

This paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one.

Bio

I have a bachelor’s degree in Computer Engineering from the Universitat de Girona (UdG) and I am currently finishing my master’s degree in Innovation and Research in Informatics in High Performance Computing from the Universitat Politècnica de Catalunya, Facultat d’informàtica de Barcelona (UPC-FIB). About three years of experience in AI applied in healthcare, working in the eXiT research group of the UdG. I have done my Master’s thesis at UPC-FIB on the first implementation of the hypervisor extension in a RISC-V processor. Currently I am working at Semidynamics and actively participating in the European Vitamin-V project.

Lawrence Hunter – QEMU Vector Cryptography extension support

Lawrence Hunter (Codethink, Manchester, United Kingdom) , Nazar Kazakov, Kiran Ostrolenk.

Poster #23 in MR12-13-14 on Thu 8th. Link: poster.

Kenneth Rovers – The landscape of RISC-V floating point support with BF16 at the centre

Kenneth Rovers (Imagination Technologies, Sint-Michielsgestel, Netherlands)

Poster #24 in MR12-13-14 on Thu 8th. Link: extended abstract.

Summary

There is a bewildering amount of number formats, particularly floating point ones. Each ISA will need to consider which to support. For RISC-V, we argue we need to consider supporting all, but ratify only a few; the ones that have become mainstream. Current ratified extensions of the RISC-V ISA suffices, with the exception of BF16 (Brain floating point format) support (and perhaps rising star FP8). Supporting BF16, however, is also not straightforward. We will identify several use cases; as a storage format, for efficient computations, and as an arithmetic format, and expose BF16 is not a standard, highlighting differences in implementations. For RISC-V support we need to balance flexibility with (hardware) efficiency and will recommend complementary extensions with the base supporting flushing subnormal numbers and round-to-zero.

Bio

Kenneth Rovers is CPU architect at Imagination Technologies committed to achieving the best possible RISC-V CPUs and defining its future, with a focus on compute. Previously leading the datapath team, he is an expert on processing architectures and datapath, including floating point arithmetic, vector processing, GPU shader ALUs, texture processing, and AI convolution engines. Kenneth received his PhD on computer architecture for embedded systems in 2011 from the University of Twente, the Netherlands, covering many-core architectures, dataflow processing, and model-based design using executable mathematics. He also holds a MSc in computer science and a MSc in electrical engineering from the same university

Guy Lemieux – RVV-lite v0.5: A Modest Proposal for Reducing the RISC-V Vector Extension

Guy Lemieux (University Of British Columbia, Vancouver, Canada)

Poster #25 in MR12-13-14 on Thu 8th. Link: extended abstract.

Bio

Guy Lemieux is a Professor in Computer Engineering at the University of British Columbia in Vancouver, Canada. Before that, he completed his PhD, MASc and BASc degrees at the University of Toronto. His PhD work established new methods for designing FPGA interconnect that are now routinely used at FPGA companies. In 2011, he co-founded VectorBlox Computing Inc., which was bought by Microchip in 2019. VectorBlox developed an FPGA-optimized accelerator that achieved speedups up to 10,000x by adding custom tensor instructions to RISC-V, ARM, MicroBlaze, and NIOS processors. He is a member of the IEEE P3109 committee on floating-point design for machine learning. In the RISC-V community, Guy has participated in the Vector and Cache Management Operation technical groups, and is co-chair of the SIG for Soft Processors.

Guy Lemieux – From CCX to CIX: A Modest Proposal for (Custom) Composable Instruction eXtensions

Guy Lemieux (University Of British Columbia, Vancouver, Canada) , Jan Gray.

Poster #26 in MR12-13-14 on Thu 8th.

Summary

The RISC-V custom instruction encoding space is an unmanaged free-for-all, leading to conflicts and inconsistencies in opcodes, naming, discovery, error handling, context management, and other incompatibilities, that impair reuse of separately authored custom (instruction) extensions and their software libraries in one system. This fragments the RISC-V ecosystem into non-interoperable solution silos. To remedy this, the proposed RISC-V Composable Custom eXtensions (CCX) Specification defines a way to allow an unbounded number of composable custom extensions to coexist and mix-and-match in new systems. As RISC-V runs out of 32b encoding space, we forsee a similar concept applied to standard extensions, CIX.

Bio

Guy Lemieux is a Professor in Computer Engineering at the University of British Columbia in Vancouver, Canada. Before that, he completed his PhD, MASc and BASc degrees at the University of Toronto. His PhD work established new methods for designing FPGA interconnect that are now routinely used at FPGA companies. In 2011, he co-founded VectorBlox Computing Inc., which was bought by Microchip in 2019. VectorBlox developed an FPGA-optimized accelerator that achieved speedups up to 10,000x by adding custom tensor instructions to RISC-V, ARM, MicroBlaze, and NIOS processors. He is a member of the IEEE P3109 committee on floating-point design for machine learning. In the RISC-V community, Guy has participated in the Vector and Cache Management Operation technical groups, and is co-chair of the SIG for Soft Processors.

Andrei Ivanov – RIVETS: An Efficient Training and Inference Library for RISC-V with Snitch Extensions

Andrei Ivanov (ETH Zurich, Zurich, Switzerland) , Timo Schneider, Luca Benini, Torsten Hoefler.

Poster #27 in MR12-13-14 on Thu 8th. Link: extended abstract.

Summary

The openness and customizability of RISC-V makes it a compelling platform for executing deep learning applications. We present a library of efficient deep learning kernels for RISC-V hardware, addressing the challenge of achieving optimal performance in both training and inference. The library adopts the Snitch extensions to RISC-V, adheres to the OneDNN interface, and offers portable baseline implementations as well as platform-specific optimizations. Our optimizations that leverage Snitch extensions allow us to achieve up to 0.87 flops per clock cycle. RIVETS is a valuable tool for deep learning practitioners and researchers using RISC-V, providing portability, compatibility with other frameworks, and a baseline for performance comparison.

Bio

Andrei obtained his Bachelor’s degree in Computer Science in 2017 and his Master’s degree in Applied Mathematics and Physics in 2019 from the Moscow Institute of Physics and Technology in Russia. While pursuing his degrees, he worked in the laboratory of Applied Computational Geophysics, where he was involved in implementing high-performance numerical solvers for geological simulations. Later, he joined ETH Zurich’s Scalable Parallel Computing Lab as a Ph.D. student, where he focused on accelerating deep learning applications on diverse hardware. Andrei’s research interests include compiler optimizations, high-performance computing, programming models for parallel computations, and algorithms.

Gabriel Busnot – Accelerating RISC V Developments Through Network-on-Chip (NoC) Automation

Gabriel Busnot (Arteris, Montigny, France) , Frank Schirrmesiter, Michael Frank.

Poster #28 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

The open-source RISC-V ISA has gained popularity due to its customizability and versatility. Its adoption presents challenges in Networks-on-Chips (NoCs) implementation, which impact performance, power consumption, and cost. This paper discusses different protocol options for RISC-V-based SoCs in the context of their unique advantages in terms of flexibility, performance, and coherency. We introduce a physically aware NoC development framework for non-cache-coherent applications. This framework enables better management of physical constraints, reducing interconnect area and power consumption. It addresses the impact of floor planning and layouts on NoC topology development and achieves up to 5X shorter turn-around time than manual iterations. Additionally, the paper introduces an IP development framework for multiprotocol AMBA CHI and ACE cache coherent interconnect.

Tamer Eren – A RISC-V-based, Multi-threaded General Purpose GPU Core

Tamer Eren (TÜBİTAK / BİLGEM, İstanbul, Turkey) , Mehmet Eyyüp Ergin, Ömer Güzel, Hasan Erdem Yantır.

Poster #29 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

The demand for Graphics processing units (GPUs) has experienced significant growth in recent years, primarily driven by advancements in artificial intelligence, cryptocurrency mining, and gaming. In order to solve the prevailing challenge of GPU availability in the market, the development of more flexible and cost-effective solutions utilizing open-source methodologies may present a viable alternative for both academic and industrial applications. Within the context of Tübitak BİLGEM, an ongoing project aims to design a multi-core, multithread GPU architecture utilizing IMF extensions of RISC-V. The initial prototype of this architecture was constructed with a single core (RISC-V IMF) and five threads, offering parametric adjustability for the end user. Functionality demonstration was performed using a Digilent Nexys A7 FPGA at a clock frequency of 100 MHz, showcasing the capabilities of the architecture by calculating triangle points and applying rasterization techniques to generate the Tübitak Bilgem logo, utilizing specific colors.

Bio

Tamer Eren received his B.E. degree in biomedical engineering from İstanbul Medipol University in İstanbul, Turkey in 2019. Additionally, he obtained a double major (B.E.) degree in electrical and electronics engineering from the same university in 2020. After completing his undergraduate studies, he pursued a Master of Science degree in electrical-electronics engineering and cyber systems, which he completed at İstanbul Medipol University in 2021. During his master’s degree, he conducted research on time-to-digital conversions for all-digital phase-locked loop systems. Tamer Eren currently works as a digital design engineer at the Integrated Circuits Design and Training Laboratory (Tütel) of The Scientific and Technological Research Council Of Türkiye (Tübitak). His research interests include designing open-source CPU and GPU architectures, accelerators, and heterogeneous systems.

Jonathan Woodruff – CHERIoT: Rethinking Security for Low-Cost Embedded Systems

Jonathan Woodruff (University of Cambridge, Cambridge, United Kingdom) , Saar Amar, Tony Chen, David Chisnall, Felix Domke, Nathaniel Filardo, Kunyan Liu, Robert Norton-Wright, Yucong Tao, Robert N. M. Watson, Hongyan Xia.

Poster #30 in MR12-13-14 on Thu 8th. Link: extended abstract.

Summary

Small embedded cores have little area, power, or performance budget to spare for security features and yet must often run code written in unsafe languages and, increasingly, are exposed to the hostile Internet. CHERIoT (Capability Hardware Extension to RISC-V for Internet of Things) builds on top of CHERI and RISC-V1 to provide an ISA and software model that lets software depend on object-granularity spatial memory safety, deterministic use-after-free protection, and lightweight compartmentalization exposed directly to the C/C++ language model2,3. This can run existing embedded software components on a clean-slate RTOS that scales up to large numbers of isolated (yet securely communicating) compartments, even on systems with under 256 KiB of SRAM.

Bio

Dr Jonathan Woodruff is a Senior Research Associate with expertise in processor architecture and microarchitecture as well as low-level software optimisation. Jonathan earned an undergraduate degree in Electrical Engineering from the University of Texas, and a Doctorate degree from the University of Cambridge. Specialising in capability processor design, he has pushed into full-system optimisations including cache hierarchy, core timing, and multi-core designs as well as explorations into major security approaches including control flow integrity and private execution.

Odysseas Chatzopoulos – Enabling Design Space Exploration of RISC-V Accelerator-rich Computing Systems on gem5

Odysseas Chatzopoulos (University Of Athens, Athens, Greece) , George Papadimitriou, Vasileios Karakostas, Dimitris Gizopoulos.

Poster #31 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

The slowdown of CMOS scaling has led to the widespread use of heterogeneous SoCs that combine general-purpose processor cores with customized accelerators. The immense growth of the RISC-V community means that more and more people are interested in using RISC-V cores in their SoCs. It is thus imperative to obtain tools that allow for fast design space exploration and modeling of these designs. In this paper we describe our effort to port gem5-SALAM, a cutting-edge pre-RTL heterogeneous SoC simulator, to incorporate general-purpose RISC-V cores. In such a way, we provide to the RISC-V community a powerful tool to design, evaluate and optimize such systems.

Bio

PhD Candidate working in the fields of energy efficiency, reliability and performance optimization of complex Systems-on-Chip.

Gerardo Bandera Burgueño – Floating Point HUB Adder for RISC-V Sargantana Processor

Gerardo Bandera Burgueño (University of Malaga) , Javier Salamero, Miquel Moretó, Julio Villalba-moreno.

Poster #32 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is a open source ISA that an important number of companies are using in their designs currently. In this paper we present a tailored floating point HUB adder that has been implemented in the Sargantana RISC-V processor.

Bio

Gerardo Bandera-Burgueño received the M.Sc. degree in Computer Engineering and the Ph.D. degree in Computer Science from the University of Málaga, Spain, in 1994 and 1999, respectively. In 1994 he was Assistant Professor of the Department of Computer Architecture at the University of Málaga. Since 2001 he is Associate Professor. In addition to regular courses, he has taught several international summer courses and some CISCO and NVIDIA seminars, where he is a certified lecturer. His research interests include heterogeneous and high-performance computing, computer arithmetic, and architectures for SIMD and vector processing. He has more than 30 contributions to international journals, conferences, and book chapters, and has participated in more than 20 national and international research projects. He has led more than 10 R&D projects with international companies.

Riccardo Alidori – Hardware Support for Variable Precision Floating Point Formats Exploration

Riccardo Alidori (CEA-List, Grenoble, France) , Andrea Bocco.

Poster #33 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

Variable Precision (VP) Floating Point (FP) is a solution to compensate accumulation and rounding errors during computing. Hardware approaches to VP FP are often preferred, since software solutions result in algorithmic performance degradation and computational instability. We propose three new VP formats and evaluate them using a RISC-V platform running on a FPGA. Preliminary results show that our VP formats are beneficial for certain applications with low-precision requirements.

Maria Ramirez Corrales – Improving Post-Quantum Cryptography coupling Near-Memory Computing and RISC-V Cores

Maria Ramirez Corrales (CEA, Grenoble, France) , Emanuele Valea, Jean Philippe Noël.

Poster #34 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

Near-Memory Computing (NMC) is a promising architectural approach to accelerate and improve the efficiency of matrix products, since it drastically reduces the transfer of data between the CPU and the data memory. In this paper, we propose to couple a NMC co-processor with a RISC-V based CPU to accelerate the matrix product in Post-Quantum Cryptography (PQC) algorithms. Experimental results on the matrix product of FrodoKEM PQC algorithm show a 4X improvement in performance with respect to the same implementation without the NMC approach.

Bio

Maria Ramirez Corrales received her Master in Industrial Engineering specialized in Electronics from the Universidad Politécnica de Madrid (Spain) in 2021. She also received a Research Master in Nanoscience and Nanotechnologies from the Ecole des Mines de Saint-Etienne (France), in 2019. She is currently a research engineer at CEA LIST Grenoble (France). Her main research interests include Near Memory Computing circuits, hardware security for embedded applications, and the development of Computational SRAMs.

Francesc Moll – Kameleon, a RISC-V based 2-core multi-accelerator academic SoC

Francesc Moll (Barcelona Supercomputing Center) , David Aguiló Domínguez, Oscar Alonso, Max Doblas, César Hernández, Vatistas Kostalampros, Santiago Marco-Sola, Abbas Haghi, Jordi Fornt, Juan Miguel De Haro, Carlos Rojas, Enrico Reggiani, Roger Figueras, Pau Fontova, Xavier Carrril, Hugo Safadi, Diego Mateo, Xavier Aragonés, Jordi Sacristán, Carmen Martínez, Ángel Diéguez, Sergio Moreno, Manuel Lopez, Fernando Arreza, Lluís Terés, Miquel Moretó, Adrián Cristal, Osman Unsal, Mateo Valero.

Poster #35 in MR12-13-14 on Thu 8th. Link: poster.

Summary

Kameleon is an SoC based on the RISC-V ISA. It integrates two cores, one of them with an out of order backend; and four accelerators: SAURIA, an accelerator for Deep Neural Networks; PQC, an encryption accelerator for secure communication; Picos, a hardware accelerated task scheduler and WFA, a genomics analysis accelerator.

Bio

David Aguiló received the B.S. degree in Automatic and Electronic Industrial Engineering in 2020, and the M.Sc. degree in Electronic Engineering in 2023, both from Universitat Politècnica de Catalunya (UPC). He started his participation in the DRAC project in 2022, with Universitat de Barcelona (UB) and Barcelona Supercomputing Center (BSC), where he is currently a Research Engineer. David was one of the members of the physical design team responsible for the Kameleon chip in the DRAC project.

Charisios Loukas – Low-latency user-level communication for RISC-V clusters

Charisios Loukas (FORTH, Herakleion, Greece) , Pantelis Xirouchakis, Michalis Gianioudis, Aggelos Ioannou, Manolis Katevenis, Nikos Chrysos.

Poster #36 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

Within the context of the RED-SEA project, we integrate novel low-cost interconnect technologies with open-source low-power, RISC-V processors. We present and measure a design that achieves sub-microsecond user-level latency on small packet generation and transmission between adjacent RISC-V cluster nodes.

Bio

Charisios Loukas works as an Electrical and Computer Engineer at the Computer Architecture and VLSI systems laboratory in the Foundation for Research and Technology Hellas, in Herakleion, since January 2021. He initially enrolled in the Physics department in ETH Zurich in 2011, but did not conclude his studies. Charisios graduated from the Technical University of Crete on 2019 with an Integrated Masters degree from the Electrical and Computer Engineering department. Although his main interrest as a student was mainly hardware, his current focus is on drivers and low level software. Charisios grew up in Kozani, but currently lives in Herakleion. He enjoys making machines work and even more so the outdoors.

Francisco Marqués da Costa – Open Source RISC-V Advanced Interrupt Architecture (AIA) IP

Francisco Marqués da Costa (University of Minho, Guimaraes, Portugal) , Manuel Rodríguez, Bruno Sá, Sandro Pinto.

Poster #37 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

This work describes the design and implementation of an open-source Advanced Interrupt Architecture (AIA) IP compliant with the RISC-V AIA specification (v1.0-RC2). We have designed and implemented the core extensions, the Advanced Platform Level Interrupt Controller (APLIC), and the Incoming Message-Signalled Interrupt Controller (IMSIC) IPs. These IPs being integrated into a RISC-V CVA6-based (64-bit) SoC. We conduct a preliminary evaluation of the system and present a hardware report. Our work showcases the feasibility of implementing RISC-V AIA and establishes a base for future research and development. We will open-source our IP to foster collaboration among the RISC-V community.

Bio

Francisco Marques da Costa is an M.Sc. student at the Embedded Systems Research Group, University of Minho, Portugal. Francisco holds a Bachelor’s in Electronics and Computer Engineering and is currently in his second year of a Master’s degree, which has specialized in Embedded Systems and Micro and Nanotechnologies. Francisco’s areas of interest include computer architecture, digital systems design, low-level programming, operating systems, and cybersecurity. Contact him at pg47200@alunos.uminho.pt

David Mallasén Quintana – PERCIVAL: Integrating Posit and Quire Arithmetic into the RISC-V Ecosystem

David Mallasén Quintana (Universidad Complutense De Madrid, Madrid, España) , Raul Murillo, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matias.

Poster #38 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

Posit arithmetic is an alternative to IEEE 754 standard floating-point that presents promising properties in areas such as high-performance computing or artificial intelligence. The open-source PERCIVAL posit RISC-V core integrates posit arithmetic and quire capabilities into hardware. In addition, Xposit, a RISC-V custom extension for posit operations allows for the compilation of C programs with inline assembly posit and quire instructions. PERCIVAL is based on the application-level CVA6 core developed by the PULP Platform and maintained by the OpenHW Group. As a study platform, it has support for both posit and IEEE 754 formats, further permitting the comparison of these arithmetic representations.

Bio

David Mallasén Quintana is a Ph.D. student in Computer Engineering at Complutense University of Madrid (UCM), where he received a BSc Degree in Computer Science and a BSc Degree in Mathematics in 2020. In 2022 he obtained a MSc Degree in Embedded Systems at KTH Royal Institute of Technology (Stockholm), specializing in embedded platforms. His main research areas include computer arithmetic, computer architecture, embedded systems, and high-performance computing.

Nils Wistoff – Towards Full Time Protection of an Open-Source, Out-of-Order RISC-V Core

Nils Wistoff (ETH Zürich, Zürich, Switzerland) , Gernot Heiser, Luca Benini.

Poster #39 in MR12-13-14 on Thu 8th. Links: extended abstract, poster.

Summary

Microarchitectural timing channels enable information transfer between security domains that are supposed to be isolated, bypassing the operating system’s security boundaries. They result from shared microarchitectural state that depends on execution in one security domain and impacts timing in another. Since modern ISAs do not specify timing behaviour, they are insufficient to address these channels. The temporal fence instruction was recently proposed as a RISC-V extension that clears the processor’s microarchitectural state and thus removes any timing dependence on execution history. It has been demonstrated to be extremely effective at low hardware overhead for in-order RV processors, such as CVA6 [1]. In this work-in-progress, we provide initial insight into the effectiveness and cost of the temporal fence on the open-source, 12-stage, out-of-order RV64GC core OpenC910. We highlight challenges that arise from the out-of-order microarchitecture of OpenC910 and propose an approach that leverages the custom Xthead extension of OpenC910 and minimises the required hardware modifications to enable time protection.

Bio

Nils Wistoff received the BSc and MSc degrees from RWTH Aachen University in 2017 and 2020, respectively. He is currently working toward the PhD degree with the Integrated Systems Laboratory of ETH Zürich. His research interests include processor and system-on-chip design and secure computer architecture. He has received the DATE 2021 Best Paper Award.

Frank Gurkaynak – 10 years of making PULP based chips

Frank Gurkaynak (Switzerland) , Luca Benini.

Poster #40 in MR12-13-14 on Thu 8th. Link: poster.

Ramon Canal – Vitamin-V: Virtual Environment and Tool-boxing for Trustworthy Development of RISC-V based Cloud Services

Ramon Canal (Universitat Politècnica De Catalunya, Barcelona, Spain) , Angelos Arelakis, Alberto Moreno, Josep Lluís Berral, Aaron Call, Stefano Di Carlo, Juanjo Costa, Dimitris Gizopoulos, Vasileios Karakostas, Francesco Lubrano, Konstantinos Nikas, Yiannis Nikolakopoulos, Beatriz Otero, George Papadimitriou, Yannis Papaefstathiou, Dionisios Pnevmatikatos, Daniel Raho, Alvise Rigo, Eva Rodríguez, Alessandro Savino, Alberto Scionti, Nikos Tampouratzis, Alex Torregrosa.

Poster #42 in MR12-13-14 on Thu 8th. Link: extended abstract.

Summary

Vitamin-V is a 2023-2025 Horizon Europe project that aims to develop a complete RISC-V open-source software stack for cloud services with comparable performance to the cloud-dominant x86 counterpart and a powerful virtual execution environment for software development, validation, verification, and test that considers the relevant RISC-V ISA extensions for cloud deployment.

Bio

Ramon Canal joined the faculty of the Computer Architecture Department of UPC in 2003. He was an Erasmus Student at the University of Bath (UK) in 1998, he worked at Sun Microsystems in 2000, and he was a Fulbright visiting scholar at Harvard University in 2006/2007 and a visiting professor at the University of Cyprus in 2019/2020. His research focuses on open architectures, reliability and security. He has attracted over 2000 references (Google Scholar) to his works. He has been program committee member in several editions of HPCA, ISCA, MICRO, DATE, HiPC, IPDPS, ICCD, ICPADS, CF. He has been co-general chair of HPCA 2016 and IOLTS 2012. He has been track co-chair for DATE 2019 and 2020. He has been financial co-chair of ETS 2022. He is currently an associate editor of the ACM Transactions on Architecture and Code Optimization (TACO) and the Journal of Parallel and Distributed Computing (JPDC).