Posters
The great plenary presentations are completed by outstanding posters, which are presented at the expo floor.
Quick link to reach posters presented each day:
Notes for poster presenters
- Preparation before the conference:
- Posters shall be printed in A0 format in portrait mode.
- Each presenter shall bring their own poster on site. For a list of copy shops in Munich, that offer poster printing, please look here
- There is no template for posters
- Make sure that the poster is easy to read from distance and attracts people, use QR codes to link to more content
- At least one author of the poster must register for the core conference (Tue-Thu)
- At the conference:
- You will mount your own poster, no own tape allowed, you will get some
- Each poster will be displayed for a full day.
- Presenters are expected to stand next to their posters during breaks
- The exhibition and poster area will be open only during breaks
Posters on Tuesday, June 25th
DevOps Meets RISC-V: A Safety-Certified Journey to Efficiency
Rafael Taubinger (IAR)
Poster stand A-01
The Integration of RISC-V Instruction Set Architecture into Automotive Applications- Challenges and Solutions
Neil Fan (Nuclei system)
Poster stand A-02
Andes’ Ecosystem Approach to Drive RISC-V Adoption in Automotive Designs
Samuel Chiang (Andes Technology)
Poster stand A-03
Atalanta: Open-Source RISC-V Microcontroller for Rust-Based Hard Real-Time Systems
Antti Nurmi (Tampere University)
Poster stand A-04
Safety Mechanisms for highly configurable RISC-V based Automotive CPU
Varadan Veeravalli (Imagination Technologies)
Poster stand A-05
Overview of a scalable test generation framework for verifying compliance with ISO26262 standard for automotive functional safety
Sanjay Menon (Software Engineer, Valtrix Systems)
Poster stand A-06
Enabling Multi-Context Execution in Machine-Mode on a RISC-V Processor
Giacomo Valente (Università degli Studi dell’Aquila)
Poster stand A-07
Hippomenes: An Experimental Implementation of the RISC-V RT Real-Time Extension
Pawel Dzialo (LTU/TUNI)
Poster stand A-08
SafeGantana: A Lockstep In-Order RISC-V Core
Marc Grau (Barcelona Supercomputing Center (BSC))
Poster stand A-09
Techniques and Tools for Fast Fault Injection Simulations of RISC-V Processors at RTL
Johannes Geier (Technical University of Munich)
Poster stand A-10
Comparison of sensitivity to soft errors, depending on ISA extensions, for RISC-V cores VeeR EH1 and EL2 from Western Digital
Daniel Leon (Universidad Francisco de Vitoria)
Poster stand A-11
Next-Gen TETRISC SoC - A Quad-Heterogeneous Design for Adaptive Fault Tolerance
Junchao Chen (IHP GmbH - Innovations for High Performance Microelectronics)
Poster stand A-12
A RISC-V-based Resilient Processing Platform for 6G Communication Networks
Marko Andjelkovic (IHP)
Poster stand A-13
SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
Michael Rogenmoser (ETH Zurich)
Poster stand A-14
Hard real time is Easy!
Pawel Dzialo (Tampere University)
Poster stand A-15
XuanTie Virtualzone Technology Undergoes Commerial Inspection
Cui Xiaoxia (Alibaba)
Poster stand B-01
SecureBOOM: Mitigating Spectre in an Out-of-Order RISC-V Core with a Formally Backed Design Flow
Tobias Jauch (RPTU Kaiserslautern-Landau)
Poster stand B-02
TrustSoC-V: An Heterogeneous SoC Architecture for RISC-V, Secure-by-Design
Raphaele Milan (LaboratoryHubertCurien)
Poster stand B-03
Fast CHERI-RISC-V Compartmentalization
Franz Fuchs (University of Cambridge)
Poster stand B-04
Into the Memory-Verse: A Multicolored Approach for C/C++ Memory Safety in RISC-V
Konrad Hohentanner (Fraunhofer AISEC)
Poster stand B-05
Spectre Mitigation through Selective Speculation Fences
Herinomena Andrianatrehina (Inria Rennes)
Poster stand B-06
Formal Verification of Security-Critical Functionality on RISC-V Processors
Christian Appold (DENSO AUTOMOTIVE Deutschland GmbH)
Poster stand B-07
ARM vs RISC-V: Code Reuse Attacks Exploitable Surface
Téo Biton (Thales)
Poster stand B-08
STANDARDIZING CHERI FOR RISC-V
Tariq Kurd (Codasip)
Poster stand B-09
Tag Management in CHERI-RISC-V Systems
Jonathan Woodruff (University of Cambridge)
Poster stand B-10
MachineWare GmbH - Virtual Hardware, Real Benefits
Lukas Juenger (MachineWare GmbH)
Poster stand B-11
Ensuring Datapath Integrity and Adherence with Formal Security Verification in RISC-V Implementation
Keerthikumara Devarajegowda (Siemens EDA)
Poster stand C-01
CHERI Is Not Just a Hardware Extension
Carl Shaw (Codasip)
Poster stand C-02
Deep Insight into IOPMP: Priority and Non-Priority Rules
Paul Ku (Andes Technology)
Poster stand C-03
Xen-Se: A Secure Extended Isolation Hypervisor for Trusted RISC-V Hardware
Zhixuan Xu (RISC-V International Open Source Lab)
Poster stand C-04
Enhancing SecureOS porting to RISC-V architecture using hypervisor
Paweł Kulig (Samsung)
Poster stand C-05
CHERI RISC-V: A Case Study on the CVA6
Bruno Sa (University of Minho - Centro ALGORITMI/LASI)
Poster stand C-06
Security, Safety, and Predictability of CHERI RISC-V for Drone Systems
Donato Ferraro (Minerva Systems SRL, University of Modena and Reggio Emilia)
Poster stand C-07
Hardware-based stack buffer overflow attack detection on RISC-V architectures
Cristiano Chenet (Politecnico di Torino)
Poster stand C-08
Hardware/Software Runtime for GPSA Protection in RISC-V Embedded Cores
Louis Savary (Inria)
Poster stand C-09
Sonata: low-cost open-source CHERI hardware for embedded systems
Marno van der Maas (lowRISC)
Poster stand C-10
METASAT Platform: High Performance Space Processing for Institutional Missions Using Multicore, GPU and AI Accelerators
Leonidas Kosmidis (Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC))
Poster stand C-11
The Performance and (Hidden) Communication Cost of Hardware Accelerators for Hash Primitives Used in Post-Quantum-Cryptography
Jonas Schupp (Technical University of Munich, TUM School of Computation, Information and Technology)
Poster stand D-01
Analyzing threats & detecting trojans through formal analysis in a semiconductor IP
Gulam Ashrafi (Synopsys)
Poster stand D-03
The CHERI-RISC-V open-source ecosystem
Peter Rugg (University of Cambridge)
Poster stand D-04
Selective Cache Re-Mapping to Mitigate Cache Side Channel Attacks on RISC-V Processors
Pavitra Bhade (Indian Institute of Technology)
Poster stand D-05
Wait a minute for RISC-V Cross-core cache attack on a real-world SoC
Kilian Zinnecker (Fraunhofer AISEC)
Poster stand D-06
Exploring the Potential of OpenTitan as a Control-Flow Integrity Coprocessor
Emanuele Parisi (Universita’ di Bologna)
Poster stand D-07
Securing Embedded and IoT Systems with SPMP-based Virtualization
Jose Martins (University of Minho)
Poster stand D-08
TitanSSL: Towards Accelerating OpenSSL in a Full RISC-V Architecture Using OpenTitan
Alberto Musa (University of Bologna)
Poster stand D-09
Impact of the four French RISC-V Contests on Education and Research
Jerome Quevremont (Thales Research & Technology)
Poster stand D-10
“One Student One Chip” Initiative: Learn to Build RISC-V Chips from Scratch with MOOC
Zihao Yu (ICT, CAS)
Poster stand D-11
Cloud-V: Becoming the first official RISC-V Lab Partner
Moiz Hussain (10xEngineers)
Poster stand D-12
Posters on Wednesday, June 26th
An Interchangeable UVM Environment for Verifying Multiple Systolic Arrays
Junaid Ahmed (Barcelona Supercomputing Center)
Poster stand A-01
Cross-Level Verification of Hardware Peripherals
Sallar Ahmadi-Pour (University of Bremen)
Poster stand A-02
Accelerating RISC-V Core Verification through scalable hybrid FPGA Co-Simulation
Stanislaw Kaushanski (MINRES Technologies GmbH)
Poster stand A-04
Efficient Architecture Verification Framework with FPGA Acceleration for RISC-V Processors
yang zhong (Institute of Computing Technology Chinese Academy of Sciences)
Poster stand A-05
Efficient Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration
yang zhong (Institute of Computing Technology Chinese Academy of Sciences)
Poster stand A-06
Coverage-driven verification methodology to verify highly configurable RISC-V core
Salaheddin Hetalani (Siemens EDA)
Poster stand A-07
A design verification perspective of testing RISC-V security architectures by modeling side channel attacks
Jevin John (Valtrix Systems)
Poster stand A-08
Insight into achieving faster time-to-market for RISC-V systems from the conceptualization of design using advanced verification methods
Raima Chemmanam (Valtrix Systems)
Poster stand A-09
Constrained-Randomised Verification of RISC-V Cores
Kun Anjalideep (Incore Semiconductors)
Poster stand A-10
Unique Program Execution Checking: Formal Security Guarantees for RISC-V Systems
Alex Wezel (RPTU Kaiserslautern-Landau)
Poster stand A-11
Towards open source RISC-V core verification with UVM and Verilator
Karol Gugala (Antmicro)
Poster stand A-12
Advanced RISC-V Verification: From Random Instructions to System Integrity
David Kelf (Breker Verification Systems)
Poster stand A-13
uFV - Functional coverage on RISC-V microcode
Deepa Palaniappan (AsFigo Technologies)
Poster stand B-01
Bounded Load/Stores in Grammar-based Code Generation for Testing the RISC-V Vector Extension
Manfred Schlaegl (Johannes Kepler University)
Poster stand B-02
Enhancing Privileged Architecture Support in RISC-V ISAC
Umer Shahid (UET Lahore)
Poster stand B-03
SPIKE as a Reference Model in RTL Simulation Verification Environments
Mike Thompson (OpenHW Group)
Poster stand B-04
Real Time additions to the CVA6 Core
Nicolas Tribie (Bosch FR)
Poster stand B-05
Application Specific ISA Extensions in RFID Edge Processing
Sammy Johnatan Carbajal Ipenza (NXP Semiconductors)
Poster stand B-06
Leveraging TVM to optimize AI models for custom HW Accelerators and RISCV extended instructions
Gilles Miet (Robert Bosch (France) SAS)
Poster stand B-07
Explorative surveying RISC-V open hardware and specifications for mixed-critical systems
Holger Blasum (SYSGO GmbH)
Poster stand B-08
Enhancing the RISC-V Firmware Development Workflow through a Flexible Tooling Environment
Christian Seifert (Technical University of Graz)
Poster stand B-09
QEMU-based CVA6 Framework for Efficient Functional Validation and Performance Evaluation
Fatma Jebali (CEA List)
Poster stand B-10
Open-Source Development Platform for RISC-V Application-Specific Instruction-Set Processors
Kari Hepola (Tampere University)
Poster stand B-11
A Methodology for Automating the Integration of User-Defined Instructions into RISC-V Systems based on the CV-X-IF Interface
Sofia Maragkou (Institute of Computer Technology, Vienna University of Technology)
Poster stand B-12
Instrument Control & Data Processing for high-reliable ‘New Space’ instruments
Gerard Rauwerda (Technolution)
Poster stand B-13
Towards Coverage Analysis for Translating Instruction Set Simulators
Karsten Emrich (Technical University of Munich)
Poster stand B-14
Open-Source at BOSC: Achievements and Challenges
Shan Liu (Beijing Institute of Open-Source Chip)
Poster stand C-01
Calibrate GEM5 to Boost Developing Xiangshan Processor
Yaoyang Zhou (Beijing Institute of Open Source Chip)
Poster stand C-02
Using Performance Simulation to Develop High Performance Computing
Itai Yarom (MIPS)
Poster stand C-03
Breaking the RISC-V MCUs ecosystem barriers
Giancarlo Parodi (Renesas Electronics)
Poster stand C-04
Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis
Simon Rokicki (Irisa)
Poster stand C-05
Accelerate RISC-V based DSA design with Virtual Platform Explorer
Hualin Wu (Terapines)
Poster stand C-06
DUTCTL: A Flexible Open-Source Framework for Rapid Bring-Up, Characterization, and Remote Operation of Custom-Silicon RISC-V SoCs
Thomas Benz (ETH Zurich)
Poster stand C-07
Towards a Flexible, Fast and Accurate Software Performance Simulation Environment for RISC-V
Conrad Foik (Technische Universität München)
Poster stand C-08
BLINDNAME: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC
Thomas Benz (ETH Zurich)
Poster stand C-09
Creating Custom RISC-V Processors Using ASIP Design Tools: A Post-Quantum Cryptography Case Study
Gert Goossens (Synopsys)
Poster stand C-10
Surfer: A Waveform Viewer as Dynamic as RISC-V
Lucas Klemmer (Johannes Kepler University Linz)
Poster stand C-11
RISC-V Opt-VP: An Application Analysis Platform Using Bounded Execution Trees
Jan Zielasko (Cyber-Physical Systems, DFKI GmbH)
Poster stand C-12
Domain Specific Acceleration with High-Level Synthesis
Russell Klein (Siemens EDA)
Poster stand C-13
AI-based Estimation of the RISC-V Execution Cycles of Application SW in Host-Compiled Simulation
Hector Posadas (Universidad de Cantabria)
Poster stand C-14
Propelling SystemVerilog into the Future: A leap Towards CIRCT Ecosystem Integration
Buyun Xu (Terapines Ltd)
Poster stand C-15
The First Study of the Impact of Codee on SiFive’s LLVM RISC-V Development Ecosystem
Manuel Arenaz (Codee)
Poster stand D-01
Bringing Tier-1 support for Rust to 64-bit RISC-V Linux.
Daniel Silverstone (Codethink Ltd)
Poster stand D-02
RISC-V open source compiler performance: Is it good enough?
Jeremy Bennett (Embecosm)
Poster stand D-03
Lessons from porting SW to riscv64
Ludovic Henry (Rivos)
Poster stand D-04
POSTER: Enabling an OpenStack-based cloud on top of RISC-V hardware.
Aaron Call (Barcleona Supercomputing Center)
Poster stand D-05
Vitamin-V: Expanding Open-Source RISC-V Cloud Environments
Ramon Canal (Universitat Politècnica de Catalunya)
Poster stand D-06
Leveraging Container Technology for Streamlined RISC-V ACT (Architecture Compatibility Testing)
James Shi (Alibaba Inc)
Poster stand D-07
RISE Technical Steering Committee Update
Jeffrey Osier-Mixon (Red Hat)
Poster stand D-08
openEuler RISC-V for 2024
Jingwei Wang (Institute of Software, Chinese Academy of Sciences)
Poster stand D-09
RISC-V Hypervisor extension formalization in Sail
Lowie Deferme (DistriNet, KU Leuven)
Poster stand D-10
Emulating Ox64 BL808 64-bit SBC in WebAssembly: Experiments with TinyEMU and Apache NuttX RTOS
Lup Yuen Lee (IoT Techie and Educator)
Poster stand D-11
A Design-Centric Open-Source Dataset for Enhanced EDA Applications in Machine Learning
Yifei Zhu (Student of TsingHua University)
Poster stand D-12
Unleashing the Power of Model-Based Design with RISC-V and RTOS
Rafael Taubinger (IAR)
Poster stand D-13
Automated Synthesis of a Multicore RISC-V SoC with Interconnect Customized for Dataflow Requirements Based on LiteX
Naouel Haggui (IETR INSA Rennes)
Poster stand D-14
Open Virtual Platforms APIs Enable High Quality, Easily Maintained RISC-V Processor Models
Larry Lapides (Synopsys)
Poster stand D-15
Posters on Thursday, June 27th
GCC 14 RISC-V Vectorization Improvements and Future Work
Robin Dapp (Ventana Micro)
Poster stand A-01
Accelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study
Marek Pikuła (Samsung R&D Institute Poland)
Poster stand A-02
Accelerating Unicode Conversions using the RISC-V Vector Extension
Olaf Bernstein (private)
Poster stand A-03
Bring your code to RISC-V accelerators with SYCL
Max Brunton (Codeplay)
Poster stand A-04
Comparing CGRAs with VPUs as RISC-V Coprocessors
Daniel Vazquez Iglesias (Universidad Politecnica de Madrid)
Poster stand A-05
High Performance and Efficiency 512-b & 1024-b VLEN Vector Processor and AI Related Accelerator
Nathan Ma (Nuclei System Technology)
Poster stand A-06
Towards Automated LLVM Support and Autovectorization for RISC-V ISA Extensions
Philipp van Kempen (Technical University of Munich)
Poster stand A-07
Optimizing Chrome V8 Using RISC-V J and Customed Instruction Extension
Qiaowen Yang (Tsinghua University)
Poster stand A-08
RISC-V: The CPU of choice for Graphics Processing Units (GPUs)
Andrew Johnston (Imagination Technologies)
Poster stand A-09
Exploring Accelerator Integration with Core-V eXtention InterFace (CV-X-IF) for Kyber
Alessandra Dolmeta (Politecnico di Torino)
Poster stand A-10
A RISC-V based accelerator for Post Quantum Cryptographic Primitives
Andrew Wilson (Silicon Austria Labs GmbH)
Poster stand A-11
Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
Nikolaos-Charalampos Papadopoulos (School of ECE, NTUA)
Poster stand A-12
VRP: a Variable Precision Accelerator for Scientific Computing Applications
Andrea Bocco (Univ. Grenoble Alpes, CEA, List F-38000 Grenoble, France)
Poster stand A-13
ISA Support for Hardware Resource Partitioning in RISC-V
Nils Wistoff (ETH Zurich)
Poster stand A-14
Deploying Neural Networks on RISC-V with VPU
Marius Monton (Universitat Autonoma de Barcelona)
Poster stand B-01
PerfXLM: A LLM Inference Engine on RISC-V CPUs
Chiyo Wang (PerfXLab Technologies)
Poster stand B-02
MobileBERT on RISC-V: Leveraging IREE Compiler and ACE-RVV Extension for Softmax Acceleration
Yueh-Feng Lee (Andes Technology)
Poster stand B-03
Evaluating RISC-V Efficiency and Performance with AI-Based Meteorological Inference
Daniel Suárez (Universidad de La Laguna)
Poster stand B-04
Towards Neuromorphic Acceleration through Register-Streaming Extensions on RISC-V Cores
Simone Manoni (University of Bologna)
Poster stand B-05
Full-stack evaluation of Machine Learning inference workloads for RISC-V systems
Debjyoti Bhattacharjee (imec)
Poster stand B-06
Optimizing Neural Network Classification On Resource Constrained Processors through Customization
Keith Graham (Codasip)
Poster stand B-07
Enhancing convolutional neural network computation with integrated matrix extension
Jim Ke (Andes Tech)
Poster stand B-08
Use of RISC-V to develop multiprocessor host subsystems for accelerated platform with In Memory computing based on NVM memories for AI inference answering functional safety requirements for industrial and automotive applications
Giulio Urlini (STMicroelectronics)
Poster stand B-09
Optimizing Data Transport Architectures in RISC-V SoCs for AI/ML Applications
Frank Schirrmeister (Synopsys)
Poster stand B-10
An Energy Efficient RISC-V based SoC Accelerator For CNN Inference
Sergio Castillo Mohedano (Lund University)
Poster stand B-11
Low-power Acceleration of CNNs using Near Memory Computing on a RISC-V SoC
Kristoffer Westring (Lund University)
Poster stand B-12
Accelerating AI on RISC-V: Optimizing BFloat16 for Improved Efficiency
Ruhma Rizwan (10xEngineers)
Poster stand B-13
Ztachip: A Multicore, Data-Aware, Embedded RISC-V AI Accelerator for Edge Inferencing
Elochukwu Ifediora (Individual RISC-V Member)
Poster stand B-14
muRISCV-NN: Improving RISC-V Vector Extension Performance with a Kernel Library
Jefferson Jones (Technical University of Munich)
Poster stand B-15
Three RISC-V SoCs in Three Years
Saman Payvar (Tampere University)
Poster stand C-01
SERV, QERV and HERV: Meet the world’s smallest RISC-V cores
Olof Kindgren (Qamcom)
Poster stand C-02
Commercializing CHERI on a Codasip A730 RISC-V application core
Andres Amaya Garcia (Codasip)
Poster stand C-03
XiangShan: Empowering Open-Source RISC-V Innovation with High Performance Processor and Agile Infrastructure
Luoshan Cai (Beijing Institute of Open Source Chip)
Poster stand C-04
Advancing SoC Design: A Groundbreaking Architecture for Minimizing Tape-Out Costs
Tong Liu (The Hong Kong University of Science and Technology (Guangzhou))
Poster stand C-05
CyberRio: An AI-Generated RISC-V CPU
Guohua Yin (TsinghuaUniversity)
Poster stand C-06
Various Automotive Application using ASIL Level RISC-V Cores
Nathan Ma (Nuclei System Technology)
Poster stand C-07
A simple open-source superscalar out-of-order RISC-V processor
Mathis Salmen (Technical University of Munich)
Poster stand C-08
Platform Orchestration with a RISC-V Tiny Controller
Sergi Alcaide (Barcelona Supercomputing Center (BSC))
Poster stand C-09
How to tape-out a 64-core RISC-V SoC in under 60 days
Frank Gurkaynak (ETH Zurich)
Poster stand C-10
The BRISKI RISC-V Barrel processor for ASIC and FPGA Implementation - one Core to rule them both
Riadh Ben Abdelhamid (Heidelberg University)
Poster stand C-11
Empowering the Future: Unveiling Next-Generation RISC-V Devices
Yuning Liang (DeepComputing)
Poster stand C-12
Wearable Biomarker Processing using Speckle Plethysmography based on an Embedded RISC-V ASIP
Stephan Nolting (Fraunhofer IMS)
Poster stand C-13
CVA6-Platform for RISC-V Software Development
Duncan Bees (OpenHWGroup)
Poster stand C-14
RISC-V for HPC: Where we are and where we need to go
Nick Brown (EPCC at the University of Edinburgh)
Poster stand C-15
Device Assignment with the RISC-V IOMMU
Andrew Jones (Ventana Micro Systems Inc.)
Poster stand D-01
A Rocket Core with Radar Signal Processing Accelerators as Memory-Mapped I/O Devices
Vladimir Milovanović (NOVELIC d.o.o.)
Poster stand D-02
Open-source RISC-V Input/Output Physical Memory Protection (IOPMP) IP
Luis Cunha (University of Minho)
Poster stand D-03
We had 64-bit, yes. What about second 64-bit?
Mathieu Bacou (Télécom SudParis)
Poster stand D-04
Accelerating and securing compute-intensive applications using RISC-V extensibility
Andy Frame (VyperCore)
Poster stand D-05
Enhanced LPDDR4X PHY in 12nm FinFET
Johannes Feldmann (University of Kaiserslautern)
Poster stand D-06
RADLER: RISC-V Autonomous Driving LEvel fouR hardware/software co-design
Leonidas Kosmidis (Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC))
Poster stand D-07
Asymmetric Linux-RTOS multiprocessing for RISC-V
Antti Takaluoma (Offcode oy)
Poster stand D-08
A Static Multi-Issue Fused In-Order RISC-V Vector CPU Arch. For High Efficient Real-Time Computing
Cruise Huang (acemicro)
Poster stand D-09
Maximizing Efficiency: Writing Power-Efficient RISC-V Code
Rafael Taubinger (IAR)
Poster stand D-10
Analysis Framework for ISA Optimization
Andreas Hager-Clukas (Hochschule München)
Poster stand D-11
Optimizing Software for RISC-V
Nathan Egge (Google)
Poster stand D-12