Welcome

The RISC-V Summit Europe is the premier event that connects the European movers and shakers - from industry, government, research, academia and ecosystem support - that are building the future of innovation on RISC-V.

RISC-V, the open standard instruction set architecture (ISA), is enabling a range of new applications and research that will define the future of computing in Europe. The region has been central to RISC-V’s success, with one-third of RISC-V’s global community based in Europe.

RISC-V Summit Europe takes place from Monday 24th to Friday 28th June, 2024. The combination of strong industrial and academic communities is key to the success of RISC-V in Europe, and for this reason the conference is designed to help attendees to explore both commercial and research applications. RISC-V Summit Europe is an opportunity not to be missed. Come to Munich to be part of the new wave of European computing innovation!

Keynotes & Invited Talks

Learn about the exciting progress of RISC-V across industries and the hardware/software stack from our keynote speakers and invited talks.

Thomas Böhm
Infineon Technologies

Senior Vice President & General Manager Microcontroller Automotive

Krste Asanović
SiFive

Chief Architect

Johanna Baehr
Fraunhofer AISEC

Research Associate

Edward Wilford
Omdia

Senior Principal Analyst

Larry Wikelius
RISE

Director

Alexander Kocher
Quintauris

CEO

Frank K. Gurkaynak
ETHZ

Senior Scientist

Jean Roch Coulon
Thales Group

RISC-V Architect

Philipp Tomsich
VRULL

Founder & Chief Technologist

Georgi Kuzmanov
Programme Officer

Chips Joint Undertaking

Teresa Cervero
Barcelona Supercomputing Center

Senior Researcher

Program

The exciting program of RISC-V Summit Europe spans an entire week.

Hackathon

RISC-V International is excited to join with its members Codasip and Renesas to host an in person hackathon at RISC-V Summit Europe!

For details and updates please visit the Hackathon Event website.

Panels

Two exciting panels will bring together experts to discuss the future of computing with RISC-V.

Accelerating AI Innovation with RISC-V

Invited Introduction Presentation

Philipp Tomsich
VRULL

Founder & Chief Technologist

RISC-V: Charting the Future of AI/ML with Open Standards and Global Collaboration
Introduction presentation by Philipp Tomsich, VRULL
AI is a fast evolving space, and realising its huge potential requires levels of compute innovation only possible with RISC-V. This session brings prominent members of the RISC-V AI ecosystem together to explore how the RISC-V ISA will form the common language for AI innovation, how it can deliver the performance and efficiency necessary across applications from the edge to the cloud, and the potential of software and hardware codesign. The RISC-V ecosystem is already delivering the technologies that will underpin the future of AI, come to this session to find out more!

Moderated by: Philipp Tomsich, RISC-V International and VRULL

Panelists

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Gianna Paulin
Axelera AI

Computer Architecture Engineer

Roger Espasa
Semidynamics

Founder & CEO

Xie Tao
Peking University

Chair of the RISC-V AI/ML SIG

Iakovos Stamoulis
Think Silicon S.A.

Senior Product Development Director & Co-founder

How can Europe engage more in RISC-V?

Invited Introduction Presentation

Georgi Kuzmanov
Programme Officer

Chips Joint Undertaking

Chips JU and RISC V - vision, actions, challenges
Introduction presentation by Georgi Kuzmanov, Chips JU

Moderated by: Stefan Wallentowitz, RISC-V International and Hochschule München

RISC-V holds significance for Europe due to its potential to foster innovation, enhance technological sovereignty, and stimulate economic growth within the region. By embracing RISC-V, European countries can reduce their dependency on foreign technologies and proprietary architectures, thereby enhancing their autonomy in critical sectors such as telecommunications, cybersecurity, and data processing.

However, to fully realize the benefits of RISC-V, Europe must engage more actively in the development and deployment of RISC-V technologies. This panel will explore the opportunities and challenges that Europe faces in adopting RISC-V, and discuss strategies to promote the widespread adoption of RISC-V within the region.

Panelists

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Alexandra Kourfali
EuroHPC Joint Undertaking

Programme Manager Research and Innovation

Christian Reitberger
Matterwave Ventures

Partner

Peter Gielda
Antmicro

CEO

Teresa Cervero
Barcelona Supercomputing Center

Senior Researcher