Welcome

The RISC-V Summit Europe is the premier event that connects the European movers and shakers – from industry, government, research, academia and ecosystem support – that are building the future of innovation on RISC-V.

RISC-V, the open standard instruction set architecture (ISA), is enabling a range of new applications and research that will define the future of computing in Europe. The region has been central to RISC-V’s success, with one-third of RISC-V’s global community based in Europe.

RISC-V Summit Europe takes place in Paris from Monday 12th to Thursday 15th May, 2025. The combination of strong industrial and academic communities is key to the success of RISC-V in Europe, and for this reason the conference is designed to help attendees to explore both commercial and research applications. RISC-V Summit Europe is an opportunity not to be missed. Come to Paris to be part of the new wave of European computing innovation!

Summit Overview

Get up to speed on Monday and dive into three days of RISC-V news!

Keynotes & Invited Talks

Learn about the exciting progress of RISC-V across industries and the hardware/software stack from our keynote speakers and invited talks.

RISC-V State of the Union

Talk P1.2.1, part of plenary session starting at Tuesday 13 at 11h30, in Gaston Berger amphitheater.

By Krste Asanović, SiFive, Chief Architect.

Abstract: In this session RISC-V’s Chief Architect will give an overview of RISC-V adoption across computing markets from Embedded to AI. Krste will discuss new developments in the RISC-V ISA, including security extensions and matrix extensions for AI, as well as new profile and platform initiatives.

Bio: Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-­V ISA project at UC Berkeley, serves as chairman of RISC-V International, and co­founded SiFive Inc. to support commercial use of RISC­-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.

Sovereignty, independence, innovation: 7 years of HW/SW codesign with RISC-V at CEA

Talk P1.1.4, part of plenary session starting at Tuesday 13 at 09h00, in Gaston Berger amphitheater.

By Thomas Dombek, CEA, Head of Digital Integrated Circuits and Systems Department.

Abstract: By ending the epoch of closed, proprietary ISAs, RISC-V has opened a new era of innovation in the computing world. Its open ISA not only enables the tailoring of architecture to various application domains, from performance to low power, and from safety to security, but it also enables new forms of joint initiatives in the design and tools ecosystem. This ranges from new forums of cooperation between industrial competitors in the market, to new models of industry/academic collaboration. The versatility of open ISA specifications, which enables both open-source, public cooperation and also closed-door commercial agreements, will facilitate new kinds of partnerships and unexpected advances in the computing field at large. This talk will provide a return of experience from seven years of commitment to the RISC-V ecosystem and, a peek at key achievements of CEA and its academic and business partners.

Bio: Thomas Dombek is head of the Digital Systems and Integrated Circuits division at CEA LIST (French Atomic Energy Commission), Saclay, France. He received his master’s degrees in engineering from Ecole Centrale de Lyon, France, and in microelectronics from the Technical University of Darmstadt, Germany, in 1998. He has worked over 15 years in the semiconductor industry at various research and management positions within Philips, NXP and ST-Ericsson France. In 2011, he joined CEA LIST, heading research on software, modeling and hardware challenges in smart embedded systems.

Beyond Innovation: RISC-V’s Path to Mass Adoption with Mature IP.

Talk P1.2.4, part of plenary session starting at Tuesday 13 at 11h30, in Gaston Berger amphitheater.

By Wei-Han Lien, Tenstorrent, Chief Architect and Senior Fellow.

Bio: Wei-Han Lien is a Chief Architect and Senior Fellow in Machine Learning hardware architecture. He is currently leading an architecture team in defining a high-performance RISC-V CPU, fabric, system caching, and high-performance memory subsystem for the Tenstorrent heterogeneous high-performance computation platform for AI and HPC computing. He is also leading the definition of Tenstorrent’s chiplet architecture for constructing scalable, configurable, and composable SiP with cohesive power management, security, and system management architectural definitions for compatibility.Before joining Tenstorrent, Wei-Han joined Apple through the PA Semi acquisition. He led Apple design team on the microarchitectural definitions of two of the most transformative Apple iPhone/iPad application processors from scratch, the A6 and A7 CPU projects. The Apple A7 CPU core is a solid CPU microarchitecture substrate for future generations of A-series (A7-A14) iPhone/iPad mobile processors and M-series (M1) MacBookPro processors. Before Apple, he was a distinguished architect leading P.A.Semi’s PWRficient PA6T dual O-o-O triple-issue superscalar PowerPC CPU cores. At Raza Microelectronics, he led the microarchitectures of the single-chip 40Gb scalable shared-memory switching chip and distributed-shared-memory cache coherent Ethernet switch. He joined Nexgen and AMD after graduating from the University of Michigan; he was part of a team designing the Nx586 (AMD K6), the most competitive microprocessor product to the Intel Pentium processor from 1997-1999 in the market.

Enhancing your RISC-V SoC debug and optimization with embedded functional monitors

Talk P1.2.2, part of plenary session starting at Tuesday 13 at 11h30, in Gaston Berger amphitheater.

By Mat O’Donnell, Siemens, Software Architect Lead.

Abstract: A modern RISC-V SoC may have up to several thousand embedded processor cores, running highly optimized software workloads in the field. Time-to-market pressures, system performance and in-field reliability requirements drive a need for high visibility into large fleets of deployed devices executing real-life software workloads. Traditional debug solutions are typically not built for the complexity seen in today’s complex SoCs. In this presentation, we will explain how a scalable system of embedded functional monitors combined with embedded and host/cloud based analytic software can provide actionable data and insights that helps debug, validate, and optimize RISC-V SoC devices and systems from lab bring-up to reliable large scale deployment.

Bio: Mat O’Donnell is a Software Architect Tech Lead at Tessent Embedded Analytics, Siemens EDA. Mat has 25 years of experience working in the Software Industry across multiple successful startups. In March 2017 Mat joined Tessent Embedded Analytics providing software solutions for its embedded silicon IPs where he leads a team of engineers specializing in efficient host-based software support for functional monitoring.

A cloud first: Scaleway's RISC-V servers

Talk P2.1.1, part of plenary session starting at Wednesday 14 at 09h00, in Gaston Berger amphitheater.

By Fabien Piuzzi, Scaleway.

RISC-V open designs and contributions to hardware security research and development activities

Talk P3.4.1, part of plenary session starting at Thursday 15 at 16h30, in Gaston Berger amphitheater.

By Éric Saliba, ANSSI, Head of Scientific & Technical Division.

Abstract: This presentation provides a perspective on the technical challenges of securing components and the opportunities offered by open designs based on RISC-V, giving some recent examples of ANSSI contributions to open source projects or funded projects.

Bio: Éric Saliba is head of the Scientific and Technical Division of the French National Agency for Information Systems Security (ANSSI), which brings together laboratories that contribute to the definition and maintenance of the Agency’s technical guidelines and recommendations, and provides their expertise to its beneficiaries. Eric had worked for over twenty years on upstream studies and major research and development projects, both as an expert and technical manager.

RISC-V: Reaching New Orbits in Space Computing

Talk P3.2.1, part of plenary session starting at Thursday 15 at 11h30, in Gaston Berger amphitheater.

By Lucana Santos, ESA.

Bio: Lucana Santos received the degree in telecommunication engineering from the University of Las Palmas de Gran Canaria, in 2008, and the Ph.D. degree from the Integrated System Design Division, IUMA, in 2014. She was a Visiting Researcher with the European Space Research and Technology Centre, The Netherlands. She has participated actively in industrial projects in the field of hardware architectures for hyperspectral and multispectral image compression on GPUs and FPGAs for Thales Alenia Space España and the European Space Agency. Since 2018, she has been with the Data Systems and Microelectronics Division, European Space Agency. She is currently a member of the CCSDS Multispectral/Hyperspectral Data Compression Working Group. She has coauthored several scientific articles and has been a Reviewer of major international journals in her research areas. Her current research interests include hardware architectures for on-board data processing, reconfigurable architectures, and hardware/software co-design methodologies.

Open Source Chip Design in the European Semiconductor Strategy

Talk P3.1.1, part of plenary session starting at Thursday 15 at 09h00, in Gaston Berger amphitheater.

By Stefan Wallentowitz, Hochschule München & FOSSi Foundation, Professor.

Abstract: Open source chip design has become part of the European strategy, particularly focusing on sovereignty, design access, productivity and talent. In this presentation, you will learn about open source chip design in Europe, how RISC-V plays an integral role in there and ongoing activities.

Bio: Stefan is a professor of Computer Engineering at Hochschule München University of Applied Sciences. He serves as vice-chair of the RISC-V board of directors and is director at FOSSi Foundation. He is a long term advocate of open standards and open source chip design.

The Significance of the RVA23 Profile in Advancing RISC-V Ecosystem

Talk P3.3.1, part of plenary session starting at Thursday 15 at 14h30, in Gaston Berger amphitheater.

By Trina Watt, RIVOS.

Abstract: The RVA23 profile represents a key development in the RISC-V architecture, standardizing the 64-bit application processors ISA for seamless software portability across hardware implementations. This simplifies development and supports RISC-V adoption in areas like servers, automotive and client devices, where binary compatibility is important. This presentation will look at the impact RVA23 and the platform specifications will have on high-performance applications processors and their adoption across a range of end use cases.

Safe Software Convergence: How RISC-V will benefit from a realignment in embedded design

Talk P2.2.1, part of plenary session starting at Wednesday 14 at 11h30, in Gaston Berger amphitheater.

By Edward Wilford, Omdia, Senior Research Manager.

Program

The exciting program of RISC-V Summit Europe spans 4 days.

Monday, May 12	Member and Newcomer Day Tutorials for Newcomers and Experienced Professionals, and Technical Workgroup Meetings (members only) Venue: La Cité des Sciences et de l'Industrie, Porte de la Villette, Paris.
Tuesday, May 13 to Thursday, May 15	Main Conference Program Keynotes, Plenary Presentations, Panels, Demo Theatre, Expo, Posters, Dev Zone Venue: La Cité des Sciences et de l'Industrie, Porte de la Villette, Paris.
Friday, May 16	Side Events & Workshops Side events, such as projects meetings and workshops, can be organized on Friday, May 16th. Learn more.