Technical Working Group Meetings
Monday June 5th afternoon will be dedicated to Technical Working Group (TWG) meetings, organized by:
The room numbers for Monday 5th meetings will be published in a few days.
Please note that to attend RISC-V International TWG meetings, a personal or corporate membership is required.
|TWG||RISC-V International||OpenHW Group|
RISC-V International WG Meetings
Reminder: to attend RISC-V International TWG meetings, a personal or corporate membership is required.
The main goals of the Security Horizontal Committee are:
- Promote RISC-V as an ideal vehicle for the security community
- Liaise with other internal RISC V committees and with external security committees
- Create an information repository on new attack trends, threats and countermeasures
- Identify top 10 open challenges in security for the RISC-V community to address
- Propose security committees (Marketing or Technical) to tackle specific security topics
- Recruit security talent to the RISC-V ecosystem (e.g., into committees)
- Develop consensus around best security practices for IoT devices and embedded systems
More info at https://lists.riscv.org/g/security.
The RISC-V Common Software Interface (RVM-CSI) Special Interest Group (SIG) drives the strategy and coordinates the development of RISC-V’s Common Software Interface (CSI) for RISC-V Microcontrollers.
More info at https://lists.riscv.org/g/sig-rvm-csi.
The Code Size Reduction TG will develop a holistic solution to reducing code size, covering different profiles to be competitive with other core implementations of other architectures of a similar class.
Priority is given to small embedded cores which often have very constrained memory sizes and so code size reduction is most important for cost reduction. Larger/higher performance cores will also benefit from reduced code size.
More info at https://lists.riscv.org/g/tech-code-size.
Cryptographic Extensions TG
The Cryptographic Extensions Task Group will propose ISA extensions to the vector extensions for the standardized and secure execution of popular cryptography algorithms. To ensure that processor implementers are able to support a wide range of performance and security levels the committee will create a base and an extended specification. The base will be comprised of low-cost instructions that are useful for the acceleration of common algorithms. The extended specification will include greater functionality, reserve encodings for more algorithms, and will facilitate improved security of execution and higher performance. The scope will include symmetric and asymmetric cryptographic algorithms and related primitives such as message digests.
The committee will also make ISA extension proposals for lightweight scalar instructions for 32 and 64 bit machines that improve the performance and reduce the code size required for software execution of common algorithms like AES and SHA and lightweight algorithms like PRESENT and GOST, as well as ISA proposals regarding the use of random bits and secure key management.
The Post-Quantum Cryptography explore and recommend RISC-V Instruction Set Architecture (ISA) Extensions that enhance performance and implementation efficiency for contemporary public-key cryptography, with a focus on standard Post-Quantum Cryptography algorithms like Kyber, Dilithium, and others.
More info at https://lists.riscv.org/g/tech-pqc-cryptography.
Architectural Compatibility Test SIG
The Architectural Compatibility Test SIG defines coverage requirements for RV32I compliance tests, release compliance test format spec, release compliance suite for RV32I.
More info at https://lists.riscv.org/g/sig-arch-test.
The Automotive SIG provides a global forum for technical and strategic input into activities enabling or accelerating adoption of RISC-V related technology in the Automotive industry.
More info at https://lists.riscv.org/g/sig-automotive.
The Floating Point (FP) SIG will manage the existing FP formats and evaluate emerging formats for inclusion in the RISC-V architecture.
More info at https://lists.riscv.org/g/sig-fp.
ACT Plans and Challenges
RISC-V Academic and Training Special Interest Group
Join academics and industry to connect on how to better support professors and students in teaching and learning RISC-V.
The mission of the Academic and Training Special Interest Group is to promote RISC-V as a common platform based on an open ISA. The group supports educators and students with resources to further their education on all levels of the hardware and software stack, using the RISC-V ecosystem of solutions. The group’s aim is to increase adoption of RISC-V to prepare computer and electronic engineers for the challenges and opportunities of the future.
More info at https://lists.riscv.org/g/sig-academia-training.
Data Center SIG
The Data center SIG will provide strategy and oversight for technology sectors encompassing multiple industries and extensions in Datacenter & Cloud Computing. This SIG will identify gaps across industries and RISC-V groups and create TGs that will address these gaps.
Special Interest Group on High-Performance Computing (HPC).
More info at https://lists.riscv.org/g/sig-hpc.
The System on Chip (SoC) infrastructure Horizontal Committee contains but not limited to the components that straddle the hardware/software boundary and are necessary to boot and operate systems in every product from IOT/embedded through Data Center/Cloud and beyond. By their nature these components are also often matrixed into other committees pertaining to security, RAS, platforms, etc. The intent is to provide a robust set of specifications that product implementer’s need to be successful while minimizing duplication of effort and fragmentation of design choices in the RISC-V community.
More info at https://lists.riscv.org/g/soc-infra.
Shadow Stack and Landing Pads Task Group
The Shadow Stack and Landing Pads for Control Flow Integrity (SSLP-CFI) task group will define privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow. Specifically, for protecting backward-edges we will define a shadow stack for storing return-addresses in each privilege level. For protecting forward-edges we will design a flexible label based landing pads approach which will ensure that the execution adheres to the application’s Control-Flow Graph. The design will follow the threat model compiled in CFI-SIG and will be updated on demand.
More info at https://lists.riscv.org/g/tech-ss-lp-cfi.
Special intersest group on soft CPU.
More info at https://lists.riscv.org/g/sig-soft-cpu.
OpenHW Group WG Meetingss
OpenHW Group WG meetings are public.
Agenda review, Project release checklists.
More info at https://github.com/openhwgroup.
Hypervisor, HP Data Cache, CV-VEC, Verification Strategy.
More info at https://github.com/openhwgroup/cva6.
Publication status and next steps.
More info at https://github.com/openhwgroup/core-v-sw.
Project Overviews, Spike as a reference model in core-v-verif.
E40Pv2 RTL freeze checklist, formal verification.
More info at https://github.com/openhwgroup/cv32e40p.