Conference Program

The core of the conference will be from Tuesday June 6th, 2023 to Thursday 8th, with a single track of keynotes, technical and industrial talks, alongside an exhibition and posters showcasing the latest developments across industry and research.

Authors bios, talks abstracts, and media are down below the schedule for each of the three days:

• Tuesday June 6th.
• Wednesday June 7th.
• Thursday June 8th.

Schedule

Shortcuts to authors bios, talks abstracts, and media for each of the three days:

• Tuesday June 6th.
• Wednesday June 7th.
• Thursday June 8th.

And the videos of the presentations are available in playlists:

• Videos from Tuesday June 6th.
• Videos from Wednesday June 7th.
• Videos from Thursday June 8th.

Speakers of Tuesday June 6th

Direct access to all videos from Tuesday June 6th.

Opening

Calista Redmond, RISC-V International

Plenary on Tuesday June 6th at 9:00.

Extended Abstract Recording Slides

Welcome from the RISC-V Summit Europe Steering Committee

Christian Fabre, CEA

Plenary on Tuesday June 6th at 9:20.

Extended Abstract Recording Slides

RISC-V Summit Europe Program Overview

Daniel Müller-Gritschneder, Technical University Munich & Teresa Cervero, BSC

Plenary on Tuesday June 6th at 9:30.

Extended Abstract Recording Slides

RISC-V: The Road Ahead and Technical Update

Mark Himelstein, RISC-V International

Plenary on Tuesday June 6th at 9:45.

Extended Abstract Recording Slides

Biography

Before RISC-V international Mark Himelstein was the President of Heavenstone, Inc. which concentrated on Strategic, Management, and Technology Consulting providing hardware and software product architecture, analysis, mentoring and interim management. Previously, Mark started Graphite Systems, Inc (acquired by EMC) where he was the VP of Engineering and CTO developing large Analytics Appliances using highly integrated FLASH memory. Prior to Graphite, Mark held positions as the CTO of Quantum Corp, Vice President of Solaris development engineering at Sun Microsystems and other technical management roles at Apple, Infoblox, and MIPS.

Commercial Adoption of CORE-V Open-Source RISC-V Cores - Lessons Learned

Rick O’Connor, OpenHW Group

Plenary on Tuesday June 6th at 10:00.

Extended Abstract Recording Slides

Abstract

This talk will provide a brief overview of Open-Source HW activity across the industry, barriers to adoption of Open-Source HW and challenges associated with SoC design.  Lessons learned related to the OpenHW Group Governance model and commercial adoption of CORE-V Family of open source RISC-V cores will also be presented. The CORE-V family is an OpenHW Group project to develop, deploy, and execute pre-silicon functional verification and SoC based development kits of the CORE-V family of open-source RISC-V cores. Written in SystemVerilog, CORE-V open-source IP cores match the quality of IP offered by established commercial providers and are verified with state-of-the-art, auditable flows.

Biography

Rick O’Connor is Founder and serves as President & CEO of the OpenHW Group a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate on open source cores, related IP, tools and software projects. Previously Rick was Executive Director of the RISC-V Foundation. Founded by Rick in 2015 with the support of over 40 Founding Members, the RISC-V Foundation currently comprises more than 400 members building an open, collaborative community of software and hardware innovators powering processor innovation. With many years of Executive level management experience in semiconductor and systems companies, Rick possesses a unique combination of business and technical skills and was responsible for the development of dozens of products accounting for over $750 million in revenue. Rick holds an Executive MBA degree from the University of Ottawa, Canada and is an honors graduate of the faculty of Electronics Engineering Technology at Algonquin College, Canada.

Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive and Data Center Architectures

Balaji Baktha, Ventana Micro Systems

Plenary on Tuesday June 6th at 10:15.

Extended Abstract Recording Slides

Abstract

This presentation will explore the frontier where cutting-edge computing intersects with the rapidly evolving automotive industry. As cars become increasingly reliant on advanced technologies for safety, efficiency, and performance, new design paradigms are required. Balaji will provide an exploration of how Ventana is leveraging the power of RISC-V and chiplet technologies to revolutionize how automotive manufacturers take control of their technology supply chain and enable differentiated platforms. The session will provide insights into not only the technology itself but also into the broader implications for the automotive industry and manufacturers.

Biography

Balaji Baktha is the founder and CEO of Ventana Micro Systems, a leader in high-performance RISC-V processors. He is an experienced semiconductor executive and a serial technology entrepreneur and investor with a proven track record in founding and exiting several successful startups over more than 30 years in Silicon Valley. Balaji is a board member of RISC-V International as well as several other startups, and a Limited Partner and Senior Advisor at PE and VC funds. Prior to Ventana, Balaji was the founder and CEO of Veloce Technologies, the world’s first 64-bit ARM based high performance processor for cloud-compute (acquired by AppliedMicro). Before Veloce, Balaji was the VP and GM of the Communications Business at Marvell Semiconductor where he managed multiple product groups including compute, wired and wireless networking, and Enterprise Storage SoCs. Before Marvell, Balaji co-founded Platys, a startup that pioneered iSCSI storage networking and was subsequently acquired by Adaptec (now Microsemi). Prior to Platys, Balaji founded Shuttle Technologies (acquired by SCM Micro) to build the first digital media & storage I/O SoCs for Apple, Sony, and HP.

Data Center Workloads on RISC-V

Kumar Sankaran, Ventana Micro Systems

Demo Theatre on Tuesday June 6th at 10:40.

Bare metal AI runtime deployment and analysis for a RISC-V accelerator with Kenning, Renode and IREE

Karol Gugala, Antmicro

Demo Theatre on Tuesday June 6th at 10:55.

Abstract

Thanks to their increasing computational capabilities and the open ISA’ s ability to tailor silicon to specific use cases, RISC-V based microcontroller devices are an interesting target for Machine Learning workflows in low-power applications. To make the best of the constrained resources of MCUs, Antmicro’s Kenning open source AI/ML framework was extended with a bare-metal runtime backend, enabling use with RISC-V based devices that cannot - or don’t need to - run Linux. Kenning enables you to seamlessly develop, train, optimize and deploy ML models on various embedded targets and can automatically convert the model format between the most popular AI frameworks and optimize models for their target runtime. The metrics from the deployed models can be utilized to monitor various aspects of processing, from machine resource usage to result quality. To further improve the developer experience, Kenning has been integrated with Renode, Antmicro’s open source, deterministic simulation framework. The integration of Kenning and Renode enables a hardware-less development flow and allows for complete insight into model execution and AI accelerator utilization. Renode provides a fully automated, reproducible execution environment, allowing a CI-based development of embedded models, optimization libraries, and AI accelerators. The demo will present a complete ML model deployment flow based on Kenning, targeting Google’s Springbok RISC-V AI accelerator and leveraging the RISC-V Vector Extension, fully simulated in Renode.

Biography

Karol Gugala is Engineering Manager at Antmicro, where he leads the software team and works with open source in various contexts - digital design, AI and low level software. Open source enthusiast - involved in a wide variety of FOSS projects and is Chairman of CHIPS Alliance Tools Workgroup. He has 10+ years of experience in low level software, VHDL, Linux and Verilog.

An innovative digitally wrapped analog IP subsystem for RISC-V applications

Chris Morrison, Agile Analog

Demo Theatre on Tuesday June 6th at 11:10.

Abstract

Digital chip designers face a significant challenge when it comes to integrating the necessary analog circuitry to support their SoC designs. They can experience difficulties in obtaining appropriate analog IP for specific processes and foundries, and struggle with the integration of multiple analog IP blocks from different vendors into their systems. The integration of analog and digital at the mixed-signal boundary poses a particularly daunting and resource-intensive task, requiring specialized knowledge and tools. To address these challenges, Agile Analog present an innovative analog IP subsystem for RISC-V applications. This subsystem is designed to be customizable, and digitally wrapped, offering a novel solution that tackles many of the issues encountered by SoC designers with existing solutions. Specifically, Agile Analog’s subsystem includes a comprehensive set of analog IP components essential for a typical battery-powered IoT system, including a power management unit (PMU), a sleep management unit (SMU), and data converters. These IP components undergo thorough verification in both analog and digital environments, ensuring their reliability and performance, plus seamlessly connect to the MCU’s peripheral bus and are supplied with a SystemVerilog model, facilitating their integration into an existing SoC’s verification environment.

The RISC-V Verification Ecosystem with Open Standards and Commercial Tools

Jon Taylor - Imperas Software Ltd

Plenary on Tuesday June 6th at 11:30.

Extended Abstract Recording Slides

Abstract

The freedom of RISC-V represents both new innovations in design and also the migration of verification responsibility. This keynote highlights the challenges facing SoC teams as they adopt RISC-V and provides a perspective on how the use of new verification standards and methodologies drives down cost, quality risk, and development time.

Biography

Jon Taylor has over 20 years of experience in the semiconductor industry, working in technical areas from CPU verification to embedded software, and commercial areas including field applications and technology strategy. He has worked on multiple architectures including Arm, RISC-V and proprietary CPUs. He holds a degree from Southampton University in Electronic Engineering and is currently Director of Product Technology for Imperas working on technology to help enable the RISC-V revolution.

RISC-V customization, HW/SW co-optimization, and custom compute

Brett Cline, Codasip

Plenary on Tuesday June 6th at 11:45.

Extended Abstract Recording Slides

Abstract

If you optimize your software for a general-purpose core there is a substantial risk that your algorithms are executed inefficiently and therefore run slowly. You can address this by creating fixed-function circuits designed to perform a specific set of operations. These hardware functions can be extremely fast, but because they are hard coded, it is difficult to modify or update them. So how can you achieve flexibility and performance? By combining both approaches. A key benefit of RISC-V customization is that you can create custom instructions tailored to your specific application needs.

To pick custom instructions correctly and create efficient implementations, software and hardware teams need to collaborate. By starting work earlier on processor customization, the software team can start developing their critical algorithms and uncover much sooner those potential gains that could not be achieved if the hardware was already frozen. We call this Custom Compute, and its benefits extend beyond performance and energy efficiency. Custom Compute can also enable organizations to improve security by adding security features at the heart of the processor. A closer collaboration between hardware and software teams, supported by a strong methodology and by efficient tools, is the future standard of system design.

RISC-V is Firing on All Cylinders

Charlie Su, Andes Technology

Plenary on Tuesday June 6th at 12:00.

Extended Abstract Recording Slides

Abstract

RISC-V has been adopted with a record-breaking speed in pretty much all applications from general-purpose tiny MCUs to datacenter AI/ML accelerator SoCs. In this keynote, we will give examples of RISC-V applications and solutions to support them; in particular, we will also analyze various approaches for matrix multiplication extension to embrace AI/ML acceleration directly in RISC-V architecture. In addition, ISO 26262 certified automotive electronics solutions have been highly sought after in recent years due to multiple catalysts. In the second part of the keynote, we will talk about how RISC-V solutions address such market, some successful examples, and new technical challenges we should look into.

Biography

Dr. Charlie Su is a Cofounder, President and CTO of Andes, a 18-year pure-play CPU IP vendor. Charlie’s main focus is on product definition, development and promotion. He spent over 12 years in the Silicon Valley with various technical and management positions at Sun Microsystems, Afara Websystems, C-Cube Microsystems, SGI/MIPS, and Intergraph. He made key contributions to several successful processors such as the Sun multi-core multi-threading Ultrasparc T1 and T2 processors, the C-Cube high-performance E-series MPEG media processors, the MIPS out-of-order R10K processor, and the Intergraph Clipper VLIW processor. Prior to starting Andes, he led the CPU and DSP development in Faraday Technology as Chief Architect. Charlie obtained his Ph.D. in CS from the University of Illinois at Urbana-Champaign, M.S. in CS from National Tsing-Hua University, and B.S. in EE from National Taiwan University.

HW-SW Interface for RAS in RISC-V Architectures

Daniele Rossi, University of Pisa

Plenary on Tuesday June 6th at 12:15.

Recording

Abstract

VASCO 2 (ASIC Vehicle for Component Security) integrates innovative, patented hardware security building blocks on 22 nm FD-SOI silicon. It enables all types of standard or customized tests to validate these technologies in operational conditions in order to characterize innovative security blocks and to prepare a transfer to industry. VASCO 2 highlights the relevance and characteristics of these hardware IPs for industry by matching current challenges in hardware security: securing processors, securing and accelerating pre- and post-quantum cryptography, modelization and characterization of True Random Number Generators (TRNG), securing memories, etc. With VASCO 2, manufacturers have access to comprehensive data on hardware security IP: security level, power consumption, silicon surface area, and impact on cycle time.

OpenHW CVA6 Linux-capable, dual-core processor on Genesys2

Massimiliano (Max) Giacometti, OpenHW Group

Demo Theatre on Tuesday June 6th at 13:00.

Abstract

The design freedoms of RISC-V offer systems and SoC developers new flexibility to optimize a processor for the requirements of the target application. Now Architectural Exploration is not just about the configuration of multi-core designs, but the analysis of the application and potential advantages of custom instructions. Custom extension can boost the performance for a target class of operations, or support new multi-core communication methods.Software development with virtual prototypes is well established, but new to RISC-V is the advantage of these platforms offer to end users migrating legacy applications to the new RISC-V based device, well before silicon is available.For SoC teams optimizing a RISC-V processor they also need to address the additional challenge of RISC-V verification, open standards such as The RISC-V Verification Interface (RVVI) are helping the ecosystem support for standards-based test benches and Verification IP. This talk highlights the RISC-V models that are unifying the hardware, software, and verification teams across all phases of RISC-V projects with dependable quality and efficiency.

Biography

Jon Taylor has over 20 years of experience in the semiconductor industry, working in technical areas from CPU verification to embedded software, and commercial areas including field applications and technology strategy. He has worked on multiple architectures including Arm, RISC-V and proprietary CPUs. He holds a degree from Southampton University in Electronic Engineering and is currently Director of Product Technology for Imperas working on technology to help enable the RISC-V revolution.

VASCO 2, an ASIC to highlight the latest innovations in security of component

Mikael Carmona, CEA

Demo Theatre on Tuesday June 6th at 13:15.

Biography

Roger Espasa is the founder and CEO of Semidynamics, an IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion™ misses, both targeted at HPC and Machine Learning. In addition, Semidynamics architected and designed the Esperanto Technologies; 1024+ core machine-learning 7 nm SoC. Prior to Semidynamics, Roger was at Broadcom working on an ARMV8 wide out-of-order core. (2014-2016). Previously, Roger worked at Intel (2002-2014) developing a vector extension for the x86 ISA, initially deployed in XeonPhi (Larrabee) which then became AVX-512. Roger also led the texture sampling unit for Larrabee. Roger then worked on Knight’s Landing (14 nm) and led the core for Knights Hill (10 nm). Between 1999 and 2001 Roger worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture known as Tarantula. Roger got his PhD from UPC in 1997, has published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D Architecture, Binary translation and optimization, Branch Prediction, and Media ISA Extensions and holds 9 patents with 41 international filings.

RISC-V Models for Verification, Software Development and Architectural Exploration

Jon Taylor - Imperas Software Ltd.

Demo Theatre on Tuesday June 6th at 13:30.

Semidynamics Highly Configurable OOO Vector Unit

Roger Espasa, Semidynamics

Plenary on Tuesday June 6th at 14:00.

Extended Abstract Recording Slides

Abstract

In this talk we will disclose Semidynamics Out-of-Order RISC-V Vector unit, which is fully compliant with the RVV1.0 specification. We will disclose all the configuration options available for customers and discuss some performance data for an 8-lane configuration

RISC-V and Antmicro’s visual system designer: Everything everywhere all at once

Michael Gielda, Antmicro

Plenary on Tuesday June 6th at 14:15.

Extended Abstract Recording Slides

Abstract

RISC-V offers unprecedented freedom in designing hardware systems, prompting a renaissance in new core implementations, system building blocks and SW-HW co-design paradigms. Drawing on the experience of working with the expansive landscape of RISC-V implementations, both on the hardware and software level, Antmicro is developing a visual platform designer which helps navigate this complexity. The tool builds on the configurability of RISC-V and the our vast open source database of hardware components to let you create advanced, real-world systems which can be simulated with the open source Renode simulator and seeded with software such as Zephyr or Linux.

Thanks to Renode’s support for vector and custom instructions and integration with Google’s IREE toolchain through Antmicro’s Kenning ML framework, the designer is also a great entrypoint for hardware-accelerated ML co-design, and combined with Antmicro’s photorealistic 3D component model library and open source HW design methodology it can be used to kickstart the development of custom RISC-V based devices.

Combine cores and HW peripherals, SoCs, modules and other hardware components, all the way to heterogeneous connected systems to build, simulate and develop software for any kind of RISC-V platform. The transparency and flexibility of this comprehensive design paradigm will provide infinite possibilities for collecting both hardware and software data for efficient co-design

Enhancing the RISC-V Trace Encoder to verify the control-flow and code execution integrity

Anthony Zgheib, CEA Leti

Plenary on Tuesday June 6th at 14:30.

Extended Abstract Recording Slides

Enabling Virtualisation on RISC-V Microcontrollers

Stefano Mercogliano, University of Naples Federico II

Plenary on Tuesday June 6th at 14:45.

Extended Abstract Recording Slides

Mitigating Transient-Execution Attacks with CHERI Compartments

Franz Fuchs, University of Cambridge

Plenary on Tuesday June 6th at 15:00.

Extended Abstract Recording Slides

Safe, Secure and Reliable Computing with the NOEL-V Processor: from the De-RISC H2020 Project and onward

Jimmy Le Rhun, Thales Research and Technology

Plenary on Tuesday June 6th at 15:15.

Extended Abstract Recording Slides

Exhibition / Poster Sessions

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Plenary on Tuesday June 6th at .

The RISC-V opportunity in Automotive Electronics

Franck Bernard, Bosch

Plenary on Tuesday June 6th at 16:30.

Extended Abstract Recording Slides

Abstract

A digital transformation of the car is currently taking place, driven by powertrain electrification, increased levels of autonomy, new in-car experiences and the trend towards the Software-defined vehicle. The automotive supply chain is looking for the computing architectures that can deliver this future.

In this talk, we will examine the opportunity that Bosch sees in the RISC-V ISA and how it can be applied to future automotive challenges. We will detail architectural trends and the move from distributed to domain-centralized and then vehicle-centralized compute. The processing needs of the different in-car processing modules will be discussed, including performance requirements and the range of cores that will be required.

We will discuss the benefits that the RISC-V architecture can bring to Bosch as an automotive supplier and how Bosch is engaging with the RISC-V ecosystem to address its computing needs across both hardware and software, as well as key considerations such as Functional Safety and Security, in both the short and long term.

Biography

Franck Bernard holds an Engineer degree in control processing from Grenoble INP and a Master of Sciences in image processing from Paris Telecom Engineering school (ENST). He started his career as researcher at Philips Electronic Lab in 1990 working in medical imaging before moving as system architect mgr for 3G Chips still with Philips. He moved to semiconductor business in 2002 as Program Manager for the 3G modem with Philips Semiconductor, and was appointed as director of IC development for 4G modem with NXP and then with ST-Ericsson. Joining STMicroelectronics in 2012, he was managing the development of Smart Rear Camera IC, and spent 2 years as technical marketing manager in the STMicroelectronics ASIC business before joining Bosch Automotive Electronics in 2015. Since then he is deputy manager of the EIY group in charge of developing Digital IPs and System on Chips for the automotive business.

Developing a RISC-V Automotive Safety Island

Peter Lewin, Imagination

Plenary on Tuesday June 6th at 17:00.

Extended Abstract Recording Slides

RISC-V Trusted MCU for Functional Safety Applications

Abdoulaye Berthe, Low Power Futures

Plenary on Tuesday June 6th at 17:15.

What’s the reality of RISC-V in automotive?

Nitin Dahad, embedded.com (moderator). Andrew Frame, SiFive. Travis Lanier, Ventana. Peter Lewin, Imagination. Charlie Su, Andes. Itai Yarom, MIPS

Plenary on Tuesday June 6th at 17:30.

Recording

Join us for an Cocktail Reception in the Exhibition area, where you can connect with visitors, speakers, and our sponsors at their stands.

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Plenary on Tuesday June 6th at .

Speakers of Wednesday June 7th

Direct access to all videos from Wednesday June 7th.

Collaboration and Culture: Leveraging Diverse Strengths to Cultivate a Stronger Community

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Plenary on Wednesday June 7th at 8:00.

Abstract

It takes a global community to bring out the best of an open standard. So how do we tap into and embrace the diversity of the ecosystem to strengthen solutions around RISC-V? RISC-V is a global standard, so it requires groups around the world to find ways to bring together individuals with different skillsets and experience, in different stages in their careers, from various industries, or across different regions, and channeling their strengths to make RISC-V the standard for open computing. From projects in Europe that pull together members across industry, academia and research, to individuals that need to rally resources across a nation or a university, here’s a chance to hear from members of the global community on how they address culture. create high-performing groups and collaborate to get the most out of their teams.

Panelists:

• Dr Yungang Bao, China RISC-V Alliance (CRVA), Beijing Institute of Open-Source Chip (BOSC)
• John D. Davis, BSC
• Gianna Paulin, Integrated Systems Laboratory (IIS) / ETH Zurich
• Calista Redmond, RISC-V International, moderator.

Open RISC-V Platforms for Energy-Efficient, Scalable Computing

Luca Benini, ETH Zürich, Università di Bologna

Plenary on Wednesday June 7th at 9:00.

Extended Abstract Recording Slides

Abstract

Today’s data-parallel workloads in HPC, AI, IoT demand ever-growing performance under an (almost) constant power envelope. To address this fundamental challenge in a regime of diminishing returns from technology scaling, we must minimize overhead associated with data transfer, data-flow management, as well as instruction fetching, decoding, while introducing “controlled doses” of domain specialization. The last decade has seen the rise of open instruction sets, open architectures, and open hardware as key enablers for designing more efficient computing systems. In this talk, I share insights gained in a decade of design adventures on open-source RISC-V hardware and software for energy-efficient computing, moving from tiny, parallel ultra-low power chips to high-performance many-core chiplets, and provide a personal view on future directions.

Biography

Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita’ di Bologna. He received a PhD from Stanford University. Dr. Benini’s research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award, the 2020 EDAA achievement Award, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS Edward J. McCluskey award.

RISC-V in China: Embracing the Era of Open-Source Chip

Dr Yungang Bao, China RISC-V Alliance (CRVA), Beijing Institute of Open-Source Chip (BOSC)

Plenary on Wednesday June 7th at 9:30.

Extended Abstract Recording Slides

Abstract

RISC-V has made a significant impact on the chip industry and academia all over the world. China’s RISC-V community shares the same goals of building a shared global RISC-V ecosystem and has been one of the main contributors to the RISC-V ecosystem. In this talk, I will first summarize the status of RISC-V in China and then introduce two specific projects towards building an open-source chip ecosystem: (1) The XiangShan project targets an open-source high-performance RISC-V core (https://github.com/OpenXiangShan/XiangShan); (2) The One Student One Chip (OSOC) Initiative aims to train undergraduates by building real RISC-V chips and has already attracted about 3000 participants from 300+ universities.

Biography

Yungang Bao is a professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and is the deputy director of ICT, CAS. He also serves as Chief Scientist of Beijing Institute of Open Source Chip (BOSC) and BoD/TSC member of RISC-V International. He founded the China RSIC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His prior research works have been adopted by Alibaba, Huawei, Intel and Microsoft etc. Over the past years, he has been leading the XiangShan project and the One Student One Chip (OSOC) Initiative. He was the winner of CCF-Intel Young Faculty Award of the year for 2013 and the winner of CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.

OpenTitan: Past, Present and Future of Open Source Secure Silicon

Dominic Rizzo, zeroRISC Inc, OpenTitan

Plenary on Wednesday June 7th at 10:00.

Extended Abstract Recording Slides

Abstract

OpenTitan brought a new level of transparency to secure silicon development with its first discrete chip design, freely available today. However, OpenTitan has always had broader goals than a single discrete silicon root of trust.

This talk will discuss the entire OpenTitan family of permissively licensed design and verification IP in the broader context of creating a high quality open silicon ecosystem. I will review the current state of the project, both the upcoming commercial discrete device tapeout and forthcoming designs built from the OpenTitan IP ecosystem.

I will explore our unique Silicon Commons approach to development across diverse partners and geographies, including how our governance model – hosted by the non-profit engineering firm, lowRISC C.I.C. – created a stable community development platform. Finally, I will present how our commitment to open development led to commercial and research innovations today, concretely demonstrating the value of implementation and development transparency.

Biography

Mr. Dominic Rizzo is CEO and co-founder of zeroRISC Inc., a RISC-V start-up working in the open source silicon space. He founded the OpenTitan project, the world’s first open source silicon root of trust design, and currently serves as its Project Director. He previously developed the first FIPS 140-2 certified Enterprise U2F Security Key, and has research interests in hardening silicon against physical attacks and side channels, trustworthy authenticators, and formal methods for proof of implementation correctness. He received his BS in Aerospace Engineering from the Massachusetts Institute of Technology and his MS in Computer Science from the California Institute of Technology.

Semidynamics Vector Unit Performance Demonstration

Semidynamics Team

Demo Theatre on Wednesday June 7th at 10:40.

Abstract

In this demo session we will show the Semidynamics vector unit running several visual benchmarks and compare their performance against a core without vector unit.

RISC-V as an enabler of heterogeneous compute

Zdenek Prikryl, Codasip

Demo Theatre on Wednesday June 7th at 10:55.

Abstract

The semiconductor industry has benefited from shrinking process nodes to improve performance while reducing cost and power for many years. But this no longer holds. We can’t rely on smaller silicon geometries to achieve computational improvements. Instead, we are in a world where performance, power, and cost benefits must come from the architecture and from custom compute. With many possible specialized processor architectures, processor design automation is essential to ensure that design cycles are short and cost effective. In this demo, we will go through some examples that show how RISC-V designs are customized for computational workloads in different domains using a single, unified toolchain for processor design automation.

Andes AI Runs Everywhere with DSP/Vector/NN Libraries and AndesClarity

Warren Chen, Andes Technology

Demo Theatre on Wednesday June 7th at 11:10.

Abstract

AI applications require efficient and powerful flexible computing capabilities of the Processor. AndesCore™ DSP/SIMD Extension (RVP) and Vector Extensions (RVV) could efficiently boost the performance with respective intrinsic functions, and highly optimized DSP, Vector, and NN libraries. In this talk, we will explore the AndesCore™ AX45MPV Vector Processor and AI software stack and solutions. With the help of the AndesClarity™ pipeline visualizer and analyzer, developers could identify stall bubbles and data and resource dependencies associated with instructions and source code for further optimizations.

Biography

Warren Chen is a Senior Technical Manager at Andes Technology, where he works in the Technical Marketing Division. Warren has over 20 years of work experience ranging from embedded operating system porting, device driver, middleware, software architecture, project management, and marketing. He is excited to be part of the dynamic and growing RISC-V community.

Android on RISC-V: Progress and Updates

Lars Bergstrom, Google

Plenary on Wednesday June 7th at 11:30.

Extended Abstract Recording Slides

Abstract

In this talk, we will discuss the progress that has been made in supporting RISC-V in Android and the Android Open Source Platform (AOSP).

We will cover the following topics:

• The progress that has been made in supporting RISC-V and recently-ratified extensions and the RVA22 profile in Android and AOSP
• Updates on language support from C/C++, Rust, Java, and other languages for new RISC-V specifications targeting Android
• An overview of how we have been investing alongside the broader RISC-V ecosystem to bring production-readiness to some key open source projects

Biography

Lars Bergstrom is a Director of Engineering at Google on the Android team, working on their platform programming languages, including Java, C/C++, and Rust and the supporting tools and libraries. He also serves as Google’s Corporate Director to RISC-V International and Chair of the Board of Directors of the Rust Foundation. Before Google, he was at Mozilla Research, initially contributing to the Servo browser project and directing the integration of Rust into Firefox and the partner ecosystem. Later, he led Mozilla’s AR and VR work, shipping software and building OEM relationships on many different devices. He received his Ph.D. in Computer Science from the University of Chicago in 2013.

RISC-V’s revolutionary role for simultaneously supporting machine learning and HPC

Dave Ditzel, founder and CTO of Esperanto Technologies

Plenary on Wednesday June 7th at 12:00.

Recording

Abstract

High-end computing is undergoing revolutionary change. After many years of most high-end computers being used to serve web pages, the last decade saw a remarkable growth in the use of machine learning. Separately, HPC computers continued to grow peak flop rates, but system design was largely constrained to x86 server CPUs coupled with GPU accelerators. The thesis of this presentation is that the rise of generative-AI system is the final tipping point that will push for merged ML/HPC system design, and that RISC-V is well positioned to be able to take a leading role in this revolution.

Biography

A well-known entrepreneur and visionary in the computer and semiconductor industry, Dave was founder and CEO of Transmeta, maker of low power x86 microprocessors, raising over $600M from startup to a $6B IPO. Dave co-authored “The Case for RISC,” along with professor David Patterson. Previously, Dave was a vice president at Intel Corporation, leading advanced processor projects, and CTO at Sun Microsystems for the SPARC Technology Business. After earning a degree in Electrical Engineering and a separate degree in Computer Science, Dave did his graduate work at U.C. Berkeley under professor David Patterson.

MEDEA: Improved Memory-Level Parallelism in a decoupled execute/access vector accelerator

Umair Riaz, BSC

Plenary on Wednesday June 7th at 12:15.

Extended Abstract Recording Slides

Introducing the PolarFire® SoC Smart Embedded Vision Kit

Brian Colgan, Microchip

Demo Theatre on Wednesday June 7th at 13:00.

Abstract

The PolarFire SoC Smart Embedded Vision kit is the latest installment in the PolarFire SoC hardware family. Microchip will exhibit the kit with a video processing demo while showcasing fabric-processor design partition in the PolarFire SoC. While all processing can be done in the Microchip RISC-V (Mi-V) Microprocessor Subsystem (MSS) of PolarFire SoC, we can show the increase in performance when some processing is off-loaded to the FPGA fabric. Come see how Microchip’s newest FPGA kit is delivering RISC-V to the masses.

Designing a RISC-V SoC with the NOEL-V Processor and the GRLIB IP Library

Jan Andersson, Frontgrade Gaisler

Demo Theatre on Wednesday June 7th at 13:15.

Abstract

The talk will provide an overview of creating a SoC design using the NOEL-V processor and GRLIB IP library. The NOEL-V processor model is a RISC-V implementation that is configurable at implementation time in a range of different configurations, ranging from RV32IM to RV64GCBH. The GRLIB IP library is a library of IP cores, that also provides technology maps to FPGA and ASIC technologies, script generation support for most popular EDA tools, and template designs. The library is available under a dual licensing, allowing both free open-source implementations and designs that require traditional commercial licensing.

Secure RISC-V for Flight controller and Mission Computer

Dr. Ari Kulmala, TII

Demo Theatre on Wednesday June 7th at 13:30.

Abstract

We have implemented security-first approach to design autonomous drones including both flight controller and mission computer functions. We will share our experiences on building these devices of high complexity. We need to tackle both real time and high-performance, virtualized workloads in the same processor cluster in practice using Asynchronous MultiProcessing (AMP) mode. On top of typical Root-of-Trust based security, we have also initiated broad research in the area of Zero Trust and ways to protect the chip throughout its full lifetime, from supply chain security to tamper-protected applications.

Biography

Dr. Ari Kulmala received his Ph.D. degree in 2009 from the Tampere University of Technology (TUT).Currently he is working with System on Chip architectures & commercialization for Technology Innovation Institute (TII) of Abu Dhabi and also holds the position of Professor of Practice at Tampere University of Technology. His experience on System-on-Chip design ranges from small power mobile devices to large scale processing infrastructure devices and datacenter applications. After working 2003-2008 in Tampere University of Technology, in 2009, he joined Wireless Modem unit of Devices R&D in Nokia as technical digital ASIC project manager. After Renesas Electronics acquired the unit he worked in Renesas Mobile from 2010-2013. In 2013 he joined Nokia Networks and headed several organizations, joined in 2020 Tampere University, and in 2021 Nordic Semiconductor for heading a Digital IC site establishment.

TRISTAN: Together for RISC-V Technology and Applications

Patrick Pype, NXP

Plenary on Wednesday June 7th at 14:00.

Extended Abstract Recording Slides

Abstract

TRISTAN is a European KDT cooperation project which started in December 2022 and runs for 3 years. The overarching aim is to expand, mature and industrialize the European RISC-V ecosystem so that it is able to compete with existing commercial alternatives. This will be achieved by leveraging the Open-Source community to gain in productivity and quality. This goal will be achieved by defining a European strategy for RISC-V based designs including the creation of a repository of industrial quality building blocks to be used for SoC designs in different application domains (e.g. automotive, industrial, etc.). The TRISTAN approach is holistic, covering both electronic design automation tools (EDA) and the full software stack. The TRISTAN consortium is composed of 46 partners from industry (both large industries as well as SMEs), research organizations, universities and RISC-V related industry associations, originating from Austria, Belgium, Finland, France, Germany, Israel, Italy, the Netherlands, Poland, Romania, Turkey and Switzerland. The presentation will focus on some of the specific targets and expected results of the project and how this fits in the Europen RISC-V Open-Source Roadmap which was developed by a European Working Group and is documented in a report: ``Recommendations and roadmap for European sovereignty on open source hardware, software and RISC-V Technologies

Shaping Europe’s digital future’’)

Biography

Patrick is Director of Strategic Partnerships at NXP Semiconductors, and has held this position since 2012. He began his career at IMEC in Belgium in 1986. In 1996 he started the start-up company CoWare on hardware/software co-design which was later acquired by Synopsys. Thereafter he worked at Philips in different positions. Patrick is Chairman of the AENEAS Technical Expert Group since 2018 and he is member of the INSIDE Steering Board since 2015. He was co-chair of the overall ECSEL Strategic Research Agenda 2019-2021 and is also co-chair of the chapter on “Transport & Mobility”. Patrick was Chairman of the Engineering Alumni Association of the KULeuven from 2005-2008. Patrick has contributed several papers in two books published by Springer on “Automated Driving’’ and “Internet of Vehicles’’. He is author of the book “Zest for Opera – Unleash your Leadership”, which was published in October 2018. The book offers inspiring insights from the world of opera for leaders in business & politics, coaches, teachers and students.

Enabling Collaborative Chip Design in the RISC-V VeeR core and Caliptra RoT Project with CHIPS Alliance tools

Karol Gugala, Antmicro & Matt Cockrell, Google

Plenary on Wednesday June 7th at 14:30.

Extended Abstract Recording Slides

Abstract

Building a modern, complex, RISC-V based digital design like the Caliptra Root of Trust requires collaborative effort between multiple development teams of various backgrounds, especially in standards-based multi-organization environments like CHIPS Alliance. While in software development massive, standards-driven collaboration is a reality through open source infrastructure and tools, the digital design space often lacks the open source tooling needed to easily share and automate workflows, scale continuous integration and enable security through transparency of the development process. In this paper, we will describe how digital design tools and workflows developed by CHIPS Alliance are being used in practice in a collaborative environment as a potential template for other work in this space.

Biography

Karol Gugala is Engineering Manager at Antmicro, where he leads the software team and works with open source in various contexts - digital design, AI and low level software. Open source enthusiast - involved in a wide variety of FOSS projects and is Chairman of CHIPS Alliance Tools Workgroup. He has 10+ years of experience in low level software, VHDL, Linux and Verilog.

Enhancing Safety with RISC-V-based SPIDER Autonomous Robot:A Use-Case from the ECSEL FRACTAL Project

Joaquim Maria Castella Triginer, Virtual Vehicle Research GmbH

Plenary on Wednesday June 7th at 14:45.

Extended Abstract Recording Slides

Hybrid Simulation with Emulation for RISC-V Software Bring Up and Hardware-Software Co-Verification

Duncan Graham, Imperas Software

Plenary on Wednesday June 7th at 15:00.

Extended Abstract Recording Slides

Accelerate HPC and AI applications with RVV auto vectorization

Hualin Wu, Terapines Ltd

Plenary on Wednesday June 7th at 15:15.

Extended Abstract Recording Slides

Exhibition / Poster Sessions

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Plenary on Wednesday June 7th at .

The CORE‑V software ecosystem: Ten lessons learned from developing vendor specific compiler tool chains

Jeremy Bennett, Embecosm

Plenary on Wednesday June 7th at 16:30.

Extended Abstract Recording Slides

The European Chips Act: Enabling chip design in Europe

Matthew Xuereb, European Commission

Plenary on Wednesday June 7th at 16:45.

Extended Abstract Recording Slides

Abstract

Following the political agreement on the European Chips Act, the crucial implementation period has now started. For the aims of the Chips Act to be realised, Europe’s market share in fab-less design must grow. The keynote will focus on the Chips for Europe Initiative, where a virtual design platform is foreseen that will enable users, particularly start-ups and SMEs to have access to EDA tools and the computing resources necessary to scale-up beyond the critical “valley of death”. It is also foreseen that the platform will include an open repository that will enable access to European open-source IP. The keynote will also go through progress since the publication of the “Recommendations and roadmap for European sovereignty on open-source hardware, software and RISC-V Technologies” report and present some of the foreseen upcoming actions in this regard.

Biography

Matthew is a Policy Officer within the Microelectronics and Photonics Industry Unit of the European Commission’s DG Communications Networks, Content and Technology. where his work focuses on the implementation of Pillar 1 of the Chips Act. He joined the Commission in 2021, starting with an experience within DG BUDG, in the directorate responsible for the negotiations of the European annual budget. He is a graduate in Electrical and Electronic Engineering and European Politics, Economics and Law.

Pannel on EU & RISC-V

Calista Redmond, RISC-V (moderator). Luis-Carlos Busquets-Perez, EU Commission. John D. Davis, BSC. Roger Espasa, Semidynamics. Daniel Opalka, EuroHPC. Patrick Pype, NXP. Stefan Wallentowitz, Munich University of Applied Sciences

Plenary on Wednesday June 7th at 17:15.

Recording

Abstract

In recent years, the importance of semiconductor chip design and production in Europe has grown. Amidst the global chip shortage and geopolitical tensions, Europe has realized its significant dependency on technologies, which serve as the backbone for myriad industries ranging from automotive to industrial electronics, healthcare, and more. European actors from industry and academia have been very active and involved in R&D around RISC-V from its early days, and the importance of RISC-V has led to various research projects over the last years. RISC-V has been identified as an important piece in the puzzle of the future of chips in Europe. In this pannel, pannelists from the European Commission and leading research institutions along with both established semiconductor companies and RISC-V focused startups will discuss the state of RISC-V in Europe and future directions.

Connect with your fellow Summit attendees for an evening of food and drinks at the beautiful Estació de França

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Plenary on Wednesday June 7th at .

Speakers of Thursday June 8th

Direct access to all videos from Thursday June 8th.

SW-driven evolution of a uniquely modular and extensible ISA

Philipp Tomsich, VRULL GmbH

Plenary on Thursday June 8th at 9:00.

Extended Abstract Recording Slides

Biography

Dr. Philipp Tomsich is Chief Technologist and Founder of VRULL, a Software Engineering company building Software Ecosystems enabling next-generation silicon solutions for ARMv8 and RISC-V architectures. Philipp is an expert in runtime systems, high-assurance applications, secure/trusted boot, and embedded hardware. In Austria, Philipp is a court-certified expert on embedded systems, low-level programming, programming languages, compilers, and software performance. With VRULL, he supports RISC-V International’s mission as the Chair of the Applications & Tools Horizontal Committee. He oversees the software ecosystem outreach, standardization of Platforms, and the development of performance modeling, dynamic instrumentation, and analysis tools for RISC-V. Philipp also sits on the Board of Directors of RISC-V, continuing to empower the software ecosystem perspective within RISC-V and work towards making RISC-V the premier platform for software innovation. In his early years, Philipp held teaching and research roles at the Vienna University of Technology. He started his career as a compiler engineer at Silicon Graphics Inc., worked several years as a technology consultant in banking and government IT, and went on to found and bootstrap Theobroma Systems (a Software and Hardware engineering company offering tailored & standard modular solutions for high-assurance computing) later acquired by Cherry GmbH. Philipp holds a Master’s Degree and a Doctorate Degree in Computer Science from the Technical University of Vienna. For his contributions at RISC-V, Philipp has been awarded the 2021 RISC-V Community Contributor Award and the 2021 RISC-V Board of Directors Technical Leadership Award.

4 years of Open Source RISC-V at Thales

Thierry Collette, Thales R&T

Plenary on Thursday June 8th at 9:30.

Extended Abstract Recording Slides

Abstract

Thales has identified RISC-V as a great opportunity to master the performance, safety, security and certification of its solutions and has decided to actively contribute to these open source initiatives at different levels. After 4 years of Thales involvement, the opportunities of this technology are more important, the industrial ecosystem is being built and already products are being designed that take into account the use of RISC-V. Thales’ involvement in the OpenHW Group has collectively enabled the emergence of the CVA6 processor. Nevertheless, we must continue to meet the other challenges linked to this adventure, and thanks to the support of the European public authorities, we will be able to develop the ecosystem to integrate these new components into products more quickly. Finally, the new freedom to refine processor architectures offers new opportunities to address our future applications.

Biography

Thierry Collette is director of the Information Sciences and Techniques research group at Thales Research and Technology. The group focuses on disruptive technologies such as embedded and trusted AI, open hardware, continuum computing, quantum computing, etc, in order to facilitate their adoption and integration into future Thales products. Previously, Thierry Collette led the technology development division for embedded computing and components at CEA Leti & List for eight years. He contributed to set up the European Processor Initiative (EPI) in cooperation with industrial and academic partners. Previously, he was deputy director in charge of programs and strategy at CEA List. He holds several patents on multi-core architectures and has contributed to the creation of more than 10 startups, including Kalray and SiPearl. He holds an engineering degree in computer science and electrical engineering and a PhD in microelectronics.

A high-fidelity flow for high-performance RISC-V CPU design from scratch

Wei-han Lien, Tenstorrent

Plenary on Thursday June 8th at 10:00.

Extended Abstract Recording Slides

PERCIVAL: Integrating Posit and Quire Arithmetic into the RISC-V Ecosystem

David Mallasén Quintana (Universidad Complutense De Madrid)

Plenary on Thursday June 8th at 10:15.

Extended Abstract Recording Slides

Exhibition / Poster Sessions

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Plenary on Thursday June 8th at .

Developments in LLVM-based toolchains and tooling for RISC-V

Alex Bradbury, Igalia

Plenary on Thursday June 8th at 11:30.

Extended Abstract Recording Slides

Abstract

The ongoing development and maturation of RISC-V LLVM support has been a major success story for RISC-V software ecosystem enablement through cross-party collaboration. This talk will bring you up to date on the current status of that effort (both for scalar and vector instruction set extensions), highlighting some of the more interesting challenges along the way. Looking to the future, we’ll explore how the nature of LLVM development for RISC-V is changing as support for the standard ratified extensions matures, more hardware reaches the market, and as RISC-V support is added for additional LLVM project tools and sub-projects beyond the backend and the Clang C/C++ frontend.

Biography

Alex Bradbury is a compiler engineer at Igalia, working within a growing LLVM sub-team largely focused on RISC-V compiler support. He has been heavily involved in the RISC-V ecosystem since its inception, working across the hardware and software stack, previously co-founding lowRISC CIC. He initiated the upstream RISC-V LLVM backend implementation, authoring the initial patchset, acting as upstream code owner, and collaborating with a growing set of contributors. Alex is also well known within the LLVM community for the LLVM Weekly newsletter.

Automated Cross-level Verification Flow of a Highly Configurable RISC-V Core Family with Custom Instructions

Stanislaw Kaushanski, MINRES GmbH

Plenary on Thursday June 8th at 12:00.

Extended Abstract Recording Slides

Multi-ISA Firmware Compatibility - Bringing RISC-V and IHV Ecosystems Together

Andrei Warkentin, Intel

Plenary on Thursday June 8th at 12:15.

Extended Abstract Recording Slides

Exhibition / Poster Sessions

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Plenary on Thursday June 8th at .

RISC-V: a Rising Star in Space

Roland Weigand, European Space Agency (ESA)

Plenary on Thursday June 8th at 14:00.

Extended Abstract Recording Slides

Abstract

The European Space Agency, in a long tradition, is promoting the use of open Instruction Set Architectures (ISA). The SPARC ISA had been selected more than 25 years ago, mainly for two reasons: Firstly, because it is an open specification, warranting our non-dependence by allowing us to develop our own IP, avoiding court cases with a copyright owner. Secondly because of its significant backing from the commercial world, ensuring availability of compilers etc. Several generations of SPARC microprocessors have been developed for space, many thousands of parts used on satellites and rockets. Today, SPARC is obsolete in academia and in the commercial world, there are no more young developers coming from universities, maintaining SW tools and OS is becoming a burden for our small space community. RISC-V is an open ISA, like SPARC, but thanks to the rapidly growing developer community, active standardization, a wide choice of IP providers and its scalability, it is the preferred choice to replace SPARC in space. While the existing microprocessors continue to be supported by their suppliers, ESA recommends the space community to standardize on RISC-V across the full range of applications, from microcontroller to High Performance Computing (HPC). The talk will introduce the efforts introducing RISC-V to space and highlight some of the challenges encountered when developing microprocessors for space. Radiation effects and reliability requirements must be considered, but constraints exist also on the organisational and commercial side, space being a niche market with a small developer community and long product life cycles.

Biography

Graduated 1993 in Electrical Engineering and Semiconductor Physics from Ecole Supérieure d’Electricité (“Supélec”) in Paris / France. Worked as digital ASIC designer for Infineon in Munich and Tel Aviv in various consumer electronics projects (e.g. TV frame rate converter, DSL modem) dealing with integration of embedded DRAM and DSP cores. Joined the European Space Agency (ESA) in 2000 as a Microelectronics Engineer. In charge of various IC development projects, a predominant topic are standard microprocessors and SoC’s built around microprocessor cores, as well as radiation-hard design methodology.

Implementation of an Edge-Computing architecture based on a RISC-V core for RFID communication

Luca Lingardo, NXP

Plenary on Thursday June 8th at 14:30.

Extended Abstract Recording Slides

From CCX to CIX: A Modest Proposal for (Custom) Composable Instruction eXtensions

Guy Lemieux, University Of British Columbia

Plenary on Thursday June 8th at 14:45.

Recording

RISC-V code-size reduction with Zc extensions and dictionary compression custom instruction

Tariq Kurd, Codasip

Plenary on Thursday June 8th at 15:00.

Extended Abstract Recording Slides

RIVETS: An Efficient Training and Inference Library for RISC-V with Snitch Extensions

Andrei Ivanov, ETH Zürich

Plenary on Thursday June 8th at 15:15.

Extended Abstract Recording Slides

Exhibition / Poster Sessions

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Building commercially relevant open source silicon: The many aspects of Ibex

Gregory Chadwick, lowRISC

Plenary on Thursday June 8th at 16:30.

Extended Abstract Recording Slides

Proteus: An Extensible RISC-V Core for Hardware Extensions

Marton Bognar, imec-DistriNet, KU Leuven

Plenary on Thursday June 8th at 16:45.

Extended Abstract Recording Slides

Puma: An End-to-End Open-Source Linux-capable RISC-V SoC in 130nm CMOS

Thomas Benz, ETH Zürich

Plenary on Thursday June 8th at 17:00.

Extended Abstract Recording Slides

RISC-V Virtualization: A Case Study on the CVA6

Bruno Sá, University Of Minho

Plenary on Thursday June 8th at 17:15.

Extended Abstract Recording Slides

GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations

Yifei Zhu, Rios Lab, Tsinghua-berkeley Shenzhen Institute, Tsinghua University

Plenary on Thursday June 8th at 17:30.

Extended Abstract Recording Slides

Closing & Announcements

Calista Redmond, RISC-V International & Christian Fabre, CEA & more…

Plenary on Thursday June 8th at .

Extended Abstract Recording Slides