More than 50 keynotes, talks, panels, etc.
An event packed with news, results, demos, and networking opportunities!
The three days’ program of the core conference:
Notes for speakers are down below.
Tuesday 9
Events
Keynotes
Details
Talks
Details
Events
Details
Invited talks
Panels
Keynotes
Invited talks
Details
Talks
Welcome to the RISC-V Summit Europe 2026!
Organizers’ annoucement in Europa. On Tuesday 9, at 09h00.
Nick Kossifidis, Teresa Cervero, and Andrea Bartolini.
Abstract: The welcome address to the RISC-V Summit Europe 2026 will present the novelties of the event, provide an overview of the agenda, venue and events’ details.
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RISC-V Innovation at Scale
Keynote in Europa. On Tuesday 9, at 09h15.
Andrea Gallo.
Abstract: The RISC-V ISA and ecosystem are redefining computing, enabling new innovations in applications from the smallest, simplest embedded systems to the most demanding high performance deployments. In this session Andrea Gallo, the CEO of RISC-V International, outlines the progress of the RISC-V ecosystem in real world applications from Automotive, to Embedded, to AI and Data Center. He will outline the successes and momentum that have come from the ratification of the RVA23 profile including the latest product news from around the RISC-V ecosystem in both hardware and software enablement.
Bio: Andrea Gallo is CEO of RISC-V International. Before joining RISC-V as VP of Technology, Gallo worked in leadership roles at Linaro for over a decade as Vice President of Business Development, driving the company’s membership acquisition strategy and previously managing the Linaro Datacenter and Cloud, Home, Mobile, Networking, IoT, and Embedded Segment Groups and underlying open source collaborative projects within the Arm ecosystem. Before Linaro, Gallo was a fellow at STMicroelectronics, where he led the optimization of hardware-software architectures for new smartphone and telecommunication ICs. He also served on the board of directors for CHAOSS, a Linux Foundation project focused on the health of open source communities.
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Tailoring Workloads for Agentic AI Using Advanced Virtual Platforms for RISC-V
Keynote in Europa. On Tuesday 9, at 09h40.
Sam Grove.
Abstract: The traditional model of selecting a CPU from a datasheet and then beginning software development is outdated. Today, customers need to optimize software while being able to influence the hardware. The hardware/software co-design paradigm shift drives new requirements: system-level virtual platforms; standards-based extensible hardware; and open toolchains. This keynote will explore how virtual platforms for software development and workload optimization bridges the gap between hardware and software, enabling early architecture exploration for a variety of processor cores. Sam will explain how MIPS Atlas Explorer supports RISC-V designs that conform to standard Profiles while still allowing for application-specific extensions. He will showcase Atlas Explorer in action through demos targeting RISC-V core models and deploying to commercially available hardware. Attendees will also get a glimpse of how Atlas Explorer is being used by industry leaders to tailor systems around real workloads, reducing cost and increasing platform confidence ahead of silicon.
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Let's shift the mindset
Keynote in Europa. On Tuesday 9, at 10h00.
Cosimo Damiano Gianfreda.
Abstract: Drawing from hands-on experience building Europe’s first RISC-V HPC cluster (Monte Cimone), E4 Computer Engineering argues that RISC-V’s main barrier to industrial adoption is no longer hardware, but mindset. The community must evolve from an ISA-focused culture to a full ecosystem vision: industry-grade CPUs and accelerators, robust OS and tooling support, a solid certification program, application porting, and active engagement with industrial users, ISVs, ODMs and OEMs. Only by combining a developer-first with a customer-first approach and actively listening to industrial users can RISC-V make the leap to mainstream adoption.
Bio: Cosimo Damiano Gianfreda is one of the co-founders of E4 Computer Engineering (2002), of which he became CEO in February 2022. A passionate explorer of technological frontiers and a deep connoisseur of hardware, he previously served as CTO and brings extensive expertise in HPC, AI, and Cloud Computing, across both the Italian and European markets.
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XiangShan Practice: The Path to Industrial Deployment of Open-Source High-Performance RISC-V Processor
Keynote in Europa. On Tuesday 9, at 10h15.
YUNGANG BAO.
Abstract: XiangShan is an open-source high-performance RISC-V processor project launched in 2020. After six years of development, XiangShan has become the most active open-source hardware project internationally, with over 7,000 Stars and 900 Forks on GitHub. XiangShan is the highest-performance open-source RISC-V processor core in the world. The third-generation core, Kunminghu (KMH), supports RVA23 Profile and achieves a measured performance of 16.5 points/GHz on SPECCPU2006, reaching the level of ARM Neoverse‑N2 and meeting the requirements of data center and AI application scenarios. More importantly, XiangShan has achieved product‑level delivery and large‑scale deployment. Multiple companies have successfully taped out chips based on XiangShan and deployed them at scale, with shipments reaching 50,000 units. This talk introduces how XiangShan accelerates its iteration through agile design and achieves product‑level delivery quality through agile verification.
Bio: Yungang Bao is a professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the deputy director of ICT, CAS. Prof. Bao co-founded Beijing Institute of Open Source Chip (BOSC). His research interests include computer architecture and computer systems. He is leading the XiangShan project, which aims to build an open-source high performance RISC-V core. He launched the One Student One Chip (OSOC) Initiative in 2019. His work was published on top conferences and journals such as ASPLOS, Communication of the ACM, HPCA, ISCA, MICRO etc. and was selected to IEEE Micro Top Picks. He was the winner of RISC-V International Technical Leadership Award, CCF-Intel Young Faculty Award of the year for 2013 and the winner of CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.
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Linux on RISC-V: Learning from the Mistakes of History
Keynote in Europa. On Tuesday 9, at 11h30.
Greg Kroah-Hartman.
Abstract: Many people in the past have said “Don’t make the same mistakes that other architectures have” when it comes to the development of Linux for RISC-V. Despite this warning, many of the same things keep happening, directly affecting the future success of RISC-V. This talk will go into an opinionated description of some of these issues, and why we should learn from previous mistakes in order to save millions of dollars, and not waste precious effort.
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RVA23 Profile Support in Linux Kernel: From Extension Definitions to Userspace Export
Non-blind submission #B7EASJ in Europa. On Tuesday 9, at 12h00.
Guodong Xu and Charlie.
Abstract: RVA23, ratified by RISC-V International in October 2024, defines the mandatory extension baseline for application-class RISC-V. Eighteen months on, is the profile real inside the software stack? This talk answers from one vantage point — the Linux kernel — through a shipping part. SpacemiT’s K3 is the first mass-produced RVA23 SoC. Bringing it up in mainline (RISCstar with SpacemiT), we found the kernel’s RVA23 mandatory coverage stuck near 68% for a year, with bindings missing several extensions. Over several revisions those gaps closed, and Linux v7.0 reached 100%. From that experience, I examine how the community decides what “supporting” an extension means: a data-backed classification by whether an extension adds architectural state the OS must save and restore — showing roughly two-thirds are stateless and only need to be discoverable, not implemented. This explains the principles maintainers apply. I then cover two complementary halves now in review for v7.1. 1) Runtime detection: a unified series, carried forward from Andrew Jones’ (Qualcomm) RFC, resolving rva23u64/rva23s64 base behaviour and exporting it via /proc/cpuinfo and hwprobe. 2) Compile-time specialisation, presented by co-speaker Charlie Jenkins (Meta), builds the kernel for RVA23. I share review feedback — including Paul Walmsley’s call for hardware measurements — answered with numbers from the K3. Complete mainline RVA23 lets distributions ship generic images and reduce fragmentation; Ubuntu 26.04 has adopted it while Debian, Fedora and Red Hat wait.
Bio: Guodong Xu is a RISC-V International Advocate and Director of Software Engineering at RISCstar Solutions, with over 20 years of Linux kernel development experience. Previously at Motorola (mobile phone low-level software) and Linaro (Sr. Tech Lead, 10+ years), he now works on RISC-V upstream kernel enablement — including SpacemiT K1/K3 SoC support and RVA23 profile extensions.
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The RISE Project: Advancing the RISC-V Software Ecosystem
Non-blind submission #KMNP8Q in Europa. On Tuesday 9, at 12h15.
Nathan Egge and Ludovic Henry.
Abstract: The RISC-V Software Ecosystem (RISE) Project is a Linux Foundation Europe initiative where hardware, software and services companies collaborate to bridge the gap between architectural potential and commercial software readiness. While the RISC-V community is highly impactful, industrial-grade software often requires an extra push. RISE provides this through direct engineering, an RFP process that has already deployed over €1M in contracts, and individual support through the RISE Developer Appreciation Program. This session highlights how RISE is accelerating RISC-V adoption within key upstream open-source projects. We will detail our strategic push to enable AI/ML workloads through targeted investments in PyTorch, Llama.cpp, IREE, oneDNN, and OpenBLAS. We’ll demonstrate how RISE is lowering the barrier to entry by providing free GitHub and GitLab runners for riscv64, alongside self-service remote hardware access via the RISE Board Farm. Finally, we will share our long-term roadmap for ecosystem performance and stability, focusing on LLVM auto-vectorization for RVV at scale and the RISE Build Farm’s role in proactive bug detection across kernel, toolchain and system libraries.
Bio: Nathan Egge is a Staff Software Engineer at Google working on the native tools and libraries used to build AOSP and Android applications, including the C/C++ and Rust toolchains. He serves as co-chair of the Technical Steering Committee in RISE and previously as the chair of the System Libraries WG. Nathan received the RISC-V Board of Directors Software Leadership award in 2024 for contributions to RISC-V industry adoption.
Bio: Ludovic works at the intersection of open-source software and emerging hardware. He is a key contributor to the RISC-V ecosystem, focusing on the performance and stability of the AI stack. His recent work involves optimizing native dependencies like OpenBLAS and oneDNN and establishing the infrastructure for native PyTorch testing. Through his leadership at RISE, Ludovic is dedicated to making RISC-V a competitive, first-class platform for the next generation of AI development.
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Building the software ecosystem for a RISC-V datacenter
Non-blind submission #BTUW3M in Europa. On Tuesday 9, at 12h30.
Jon Taylor.
Abstract: The RISC-V software ecosystem has grown steadily over the last few years. For embedded software it is reasonably complete, with good compiler, RTOS, and IDE support. The Linux kernel is also well supported, with RISC-V long having upstream support, and RVA23 now supported too. Canonical moved to requiring RVA23 with the release of Ubuntu 25.10, ready for the next generation of RISC-V silicon. But building out a data center takes more than just a good desktop experience. This poster/paper will examine the other elements required including provisioning, hypervisors, containers, orchestration, and also discusses how to manage custom instructions, security, maintenance. Going beyond theory, it discusses the data center Canonical will be building to include RISC-V RVA23 silicon supporting the Launchpad.net community website as well as other uses.
Bio: Jon has 25 years of experience in the semiconductor and software industries and has been involved with RISC-V since 2019. He is currently product manager for RISC-V at Canonical driving product development to strengthen the RISC-V ecosystem.
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Lightning Round
Organizers’ annoucement in Europa. On Tuesday 9, at 12h45.
RVI.
Abstract: Abstract: RISC-V provides the ability to provide organizations of all sizes with greater flexibility and more opportunity for custom compute. We are seeing rapid adoption in a wide range of markets from automotive to mobile to data center, to aeronautics and space! Companies around the world are innovating for and on RISC-V to drive the era of open compute. In this session, we will hear directly from companies who have recently launched new solutions helping to power the era of open compute and how RISC-V helps them differentiate. These are not your ordinary product pitches. Selected companies are given tight time constraints to hit the high points and make the case for their new solution. If they go over, the audience get to clap them off stage! Presenters: Breker Systems CEA Epic Semi SiFive Tenstorrent TRISTAN / ISOLDE ESWIN Computing Xauntie
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Nuclei RISC-V Automotive Solutions: ASIL-D Safety & Full-Spectrum IP for Next-Gen Vehicles
in Demo Theater. On Tuesday 9, at 13h15.
Jianying Peng.
Abstract: This presentation introduces Nuclei’s RISC-V automotive ecosystem, delivering ISO 26262 ASIL-D safety and full-spectrum CPU IP for modern vehicle electronics. As a leading Chinese RISC-V provider, Nuclei offers scalable cores from ultra-low-power N-class to high-performance UX-class, plus NA-series automotive cores meeting ASIL-B/D requirements. With 18+ customers, 5+ mass-production projects, Nuclei’s solutions power LiDAR, radar, MCU, and ADAS applications, enabling safe, scalable RISC-V adoption for next-generation automotive systems.
Bio: CEO of Nuclei System Technology Ph.D. in Microelectronics, Zhejiang University; 20‑year CPU design & management veteran (ex‑Synopsys/Marvell). Co‑founded Nuclei (at 2018) to lead China’s RISC‑V IP innovation, delivering full‑spectrum cores and ASIL‑D certified automotive solutions. Key community leader driving RISC‑V ecosystem development and domestic semiconductor advancement.
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AIA, IOMMU and Other Flash Points: Driving RISC-V Sub-System Verification
in Demo Theater. On Tuesday 9, at 13h25.
Adnan Hamid.
Abstract: As more complex RISC-V devices emerge, the verification of the sub-systems in which they are integrated becomes more of a concern. Ensuring that overall system-level operation executes correctly is as critical as the behavior of the devices themselves. Sub-system verification is generally a complex procedure that involves multiple components, issues such as load-store behavior, coherency, performance bottlenecks and hazards, and other factors in addition to the functional behavior of the components operating together. Verifying these issues requires advanced test solutions. This talk will discuss how the requirements of this verification process may be met, which could involve processor providers and end-users. Interaction around the AIA and the IOMMU sub-system components will be leveraged to show examples of sub-system behavior verification.
Bio: Adnan is the President and CTO of Breker and the inventor of its core technology. He has over 30 years of experience in functional verification automation. Prior to Breker, he managed AMD’s System Logic Division, and also led their verification team to create the first test case generator providing 100% coverage for an x86-class microprocessor. In addition, Adnan spent several years at Cadence Design Systems and served as the subject matter expert in system-level verification, developing solutions for Texas Instruments, Siemens/Infineon, Motorola/Freescale, and General Motors. Adnan holds more than 20 patents in test case generation and synthesis. He received BS degrees in Electrical Engineering and Computer Science from Princeton University, and an MBA from the University of Texas at Austin.
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Accelerating the Future Computing with RISC-V
in Demo Theater. On Tuesday 9, at 13h35.
Li Chenxi.
Abstract: Accelerating the Future Computing with RISC-V
Bio: Accelerating the Future Computing with RISC-V
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Ascalon™ S: A RISC-V CPU for the Emerging Agentic AI Market
in Demo Theater. On Tuesday 9, at 13h55.
Gary Martz.
Abstract: As AI systems evolve from inference engines toward agentic architectures—orhcestration and execution—the CPU’s role is fundamentally changing. Agentic workloads mix branchy control-plane logic with latency-sensitive execution across heterogeneous compute. This shift creates a distinct class of CPU demand: high-throughput, compute-dense, power-efficient cores tuned for real-world AI system integration. Tenstorrent’s perspective comes from operational experience. The company ships AI workstations, servers, and software today, with RISC-V deployed at scale. Ascalon S is the product of that system-level experience applied to CPU microarchitecture. Ascalon S is Tenstorrent’s answer to the orchestration and exectuion heavy demands of agentic AI—a power and area-efficient RISC-V CPU IP core ideally built for execution swarm roles that define modern AI systems. Paired with Tenstorrent’s Innovation License, it gives customers access to RTL and key design collateral, enabling workload-specific customization, roadmap ownership, and reduced vendor lock-in. Come learn how Ascalon S and Tenstorrent’s broader IP portfolio—spanning RISC-V CPU, AI acceleration, system IP, and system interconnect—can help you own and differentiate your silicon future.
Bio: Gary Martz is Head of IP Ecosystem Strategy and IP Marketing at Tenstorrent, where he leads the company’s go-to-market and ecosystem development for its RISC-V CPU and AI IP portfolio. A veteran of the semiconductor industry, Gary previously served as Senior Director of Corporate Strategy and Ventures at Intel, where he drove initiatives in advanced technology standards for Communications Technologies, Consumer & Industrial IoT, and Automotive. He also serves on the advisory board of the University of Washington’s Industrial & Systems Engineering program and is an active senior leader in the RISC-V community. Gary holds a B.S. in Industrial Engineering from the University of Washington and an MBA in Entrepreneurial Studies from the University of Michigan.
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RISC-V Server Platform 1.0: One Spec to Boot Them All
Invited talk in Europa. On Tuesday 9, at 14h30.
Radim Krčmář.
Abstract: As RISC‑V enters high‑performance computing (from traditional data‑center servers to edge infrastructure, telecom systems, and industrial compute platforms) a unified platform definition is essential. Without a consistent hardware and firmware contract, system‑software vendors face fragmented bring‑up, slowing ecosystem adoption. The RISC‑V Server Platform Specification solves this by defining a clear baseline that supports high‑performance RISC‑V platforms. Built by composing existing standards such as the RVA23 profile, Server‑class SoC requirements, UEFI/ACPI boot via BRS, SBI interfaces, and modern security foundations including roots of trust, secure boot, attestation, and BMC‑based management, the specification enables OS and hypervisor developers to target a single portable binary. This talk outlines the goals, structure, and key requirements of Server Platform Specification 1.0, explaining how it reduces fragmentation, accelerates system‑software portability, and provides a stable foundation for interoperable, production‑ready RISC‑V platforms across diverse deployment environments.
Bio: Radim Krčmář is an engineer at Qualcomm whose work spans the lower levels of the RISC-V stack, from ISA specifications to operating system design, with a current focus on security and virtualization.
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Delivering the Future of Software Enablement for RISC-V
Panel in Europa. On Tuesday 9, at 14h45.
Abstract: Across applications from low-power embedded to High Performance Computing, the success of the RISC-V ISA is directly tied to the maturity of software support and enablement. In this panel we bring experts together from across the RISC-V ecosystem and beyond, to debate the current state of the RISC-V software enablement and discuss future priorities.
RISC-V already has strong compiler support, but what have been the most recent performance optimizations, and what do we need to prioritize in terms of next developments? What does compiler support look like for specific use cases, like safety certification for automotive, or vectorization for AI? Rust is increasing in use across Linux and Zephyr. What is the status of RUST support on RISC-V How can the RISC-V ecosystem and the Linux development team work together more efficiently? How mature is the support for the open source software ecosystem beyond compilers? What software infrastructure are we missing and what should we prioritize? What does software support look like as we move beyond profiles to platforms? What does software compatibility look like for a single ISA that scales from MCU to HPC, but relies on specific profiles and extensions? How will the use of AI in software development accelerate porting to RISC-V?
Moderator: Tom Gall - RISC-V International Panelists: Greg Kroah-Hartman - Linux Foundation Lars Bergstrom - Google Paul Carpenter - Barcelona Supercomputing Center
this panel will provide broad insight into the future of the software enablement on RISC-V!
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Epic Contrail AIX for RISC-V Developers
in Demo Theater. On Tuesday 9, at 15h45.
Chloe Jian Ma.
Abstract: Contrail AIX™ is the world’s first RISC-V AI Execution Platform, purpose-built for the next phase of artificial intelligence as the industry transitions from training models to deploying and executing intelligent applications at scale. Unlike traditional AI infrastructure, which separates CPUs for system management and GPUs for model processing, Contrail AIX is designed to support emerging workloads such as AI inference, reasoning, agentic AI, retrieval-augmented generation (RAG), autonomous systems, and physical AI, all of which require continuous orchestration, memory management, information retrieval, and workflow execution. Built on an open RISC-V architecture, the platform combines high-performance compute, AI acceleration, and a modern cloud-native software ecosystem, supporting technologies such as Ubuntu, Kubernetes, Docker, LLVM, GCC, MLIR, IREE, Ceph, and SPDK. By enabling intelligent agents to collaborate, access tools, retrieve knowledge, and execute complex tasks efficiently, Contrail AIX provides a unified and scalable foundation for the emerging AI Execution Era, where the ability to execute intelligence becomes as critical as the ability to train it.
Bio: Chloe Jian Ma is a strategic technology executive with more than 20 years of experience in AI, semiconductors, and cloud infrastructure. As Chief Business Officer at Epic Semi, she leads global growth, commercialization, and ecosystem initiatives that enable chipmakers and system innovators through agile semiconductor solutions. Prior to Epic Semi, Chloe led Edge AI and Robotics go-to-market strategy at Arm, driving strong revenue growth and expanding AI adoption across sectors including smart vision, robotics, and industrial IoT. She has also held leadership positions at SiFive, Intel, Mellanox, Juniper Networks, and Cisco Systems, where she helped build high-growth product businesses and strategic partnerships with leading cloud and AI providers. Chloe holds an MBA from the Wharton School and an MSEE from the University of Southern California. She is widely recognized for her industry leadership and commitment to advancing innovation across the global AI and semiconductor ecosystem.
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No Fab Required: Monetizing RISC-V Designs in the Cloud
Keynote in Europa. On Tuesday 9, at 16h30.
Jeremy Dahan.
Abstract: The open-standard RISC-V instruction set architecture (ISA) represents a paradigm shift in processor design and development, with its modular and customizable nature enabling a new era of processors uniquely tailored to their software workload. At RISC-V Summit 2025, AWS explored the potential of hardware / software co-design in the cloud for advanced testing and simulation, enabled by scalable, cloud-based solutions that combine high-performance FPGA instances with advanced emulation capabilities. This talk will give an update on how this democratized access is accelerating innovation cycles, reducing costs, and enabling organizations of all sizes to participate in RISC-V development, and addresses how RISC-V core developers can use AWS to monetize their designs in the cloud without the need to go to silicon.
Bio: Jeremy Dahan is an Automotive Compute Sr Tech GTM Specialist at Amazon Web Services. He’s helping customers / partners to tackle the most challenging problems related to automotive software leveraging cloud capabilities. He has over a decade of experience in the automotive industry specifically in embedded software and more recently in the cloud. When not building things on AWS, he’s tinkering with car/IoT sensors.
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Beyond Privilege: The RISC‑V Isolation Toolbox from Microcontrollers to Confidential Computing
Invited talk in Europa. On Tuesday 9, at 16h45.
Andrew dellow.
Abstract: This talk surveys the RISC‑V isolation toolbox—spanning PMP/ePMP, SPMP, privilege levels, virtualization, Risc-V Worlds, and emerging Supervisor Domains—and shows how these mechanisms can be combined to build scalable, composable security and safety systems beyond traditional privilege separation. RISC‑V has steadily developed a rich and diverse set of isolation mechanisms, including ePMP for physical memory protection, privilege levels for execution control, page‑based virtual memory for scalable address isolation, hypervisor extensions for virtualization, and Worlds for hardware‑enforced compartmentalization. Each of these tools addresses different isolation challenges, from resource‑constrained microcontrollers to full server‑class systems. Modern platforms increasingly demand fine‑grained, composable isolation rather than coarse, monolithic privilege separation. Mixed‑criticality systems, safety‑certified embedded platforms, and confidential computing environments all require isolation techniques that can be layered, combined, and adapted to different threat models and deployment constraints. This talk presents a toolbox‑oriented view of RISC‑V isolation. Supervisor Domains are introduced as an emerging architectural direction within this toolbox, exploring finer‑grained isolation within supervisor mode itself. While still evolving, Supervisor Domains illustrate the broader move beyond privilege levels toward more modular and composable execution domains and provide a useful lens for understanding how future RISC‑V systems may further decompose trusted software.
Bio: Andrew Dellow is a director in the technical standards group at Qualcomm and currently chair of the Security Horizontal Committee at RISC-V International. He is also a RISC-V Ambassador, and Chair of the SoC Infrastructure Horizontal Committee. With over 25 years’ experience in system on chip architecture and security, starting with the original development of robust Set Top Box SoCs for Pay TV, he is a former Chief Security Architect at HiSilicon Technologies, Distinguished Engineer and Technical Director at Broadcom Corp., and Security Architect at STMicroelectronics. His passion is driving secure architectures and implementations, holding more than 30 patents around SoC security.
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Why the industry needs CHERI to be able to meet the EU Cyber Resilience Act
Non-blind submission #PC8KYU in Europa. On Tuesday 9, at 17h00.
Tariq Kurd.
Abstract: The Cyber Resilience Act is fully enforced in for all products “with a digital element” sold in the EU from December 2027. It has highly stringent requirements on manufacturers, such as products being “secure by design and by default” and “having no known vulnerabilities” at the point of going on sale. Discovered vulnerabilities in the product must be reported within 24 hours for critical exploits. All vulnerabilities must be patched within a short time frame, and support must be for 5 years or longer depending on the product. As a specific example of the effect of the CRA on consumer products, the Linux kernel had 4336 reported exploits (CVEs) in 2024 (12 per day) and 5779 in 2025 (16 per day). Linux is used in an increasingly large range of consumer devices, not least a large proportion of the world’s smartphones. The able to continue to sell these products in Europe, then the industry really needs to move to a much more securely constructed systems. CHERI systems have memory safety bult-in which resolves 70% of vulnerabilities seen in weaker non-CHERI legacy systems. Resolving such a large proportion of vulnerabilities at source will greatly reduce the support and maintenance costs, if nothing else. As a result of the CRA, there will be a large shift in the industry to make systems much more secure. We expect that much of that shift will be towards CHERI systems as manufacturers wake up to the cost savings.
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Practical Implications of SPMP-Based Virtualization in RISC-V
Blind submission #XFYMDU in Europa. On Tuesday 9, at 17h15.
Manuel Rodríguez.
Abstract: The RISC-V SPMP for Hypervisor specification enable MMU-less virtualization through a multi-layered memory protection architecture. While this model provides strong isolation for mixed-criticality MCUs, concerns have been raised regarding the hardware overhead and timing impact of multiple PMP layers. In this work, we present an empirical evaluation of an SPMP for Hypervisor proof-of-concept implementation. We analyze FPGA resource utilization and timing behavior as a function of entry count and discuss realistic entry requirements for MCU-based virtualization workloads, providing insights for hardware designers adopting SPMP-based architectures.
Bio: MANUEL RODRÍGUEZ earned his M.Sc. degree in Electronic and Computer Engineering at the University of Minho, Portugal, with a focus on Embedded Systems and Micro/Nanotechnologies. He is currently pursuing a Ph.D. in Electronics and Computer Engineering at the same institution, focusing on the development of novel RISC-V ISA primitives for secure virtualization in mixed-criticality systems. Throughout his career, he has contributed to the RISC-V ecosystem providing PoC artifacts for ongoing specifications, mostly in the hardware area. His research interests encompass computer architecture, RISC-V, hardware design, embedded virtualization, and safety-critical and mixed-criticality systems.
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Enabling Confidential Computing on RISC-V: An Open-Source MPT Implementation
Blind submission #EXN7PD in Europa. On Tuesday 9, at 17h30.
Haoyuan Liu.
Abstract: Memory Protection Tables (MPT) is an emerging RISC-V extension under community discussion that enables fine-grained multi-supervisor domain physical memory isolation and access control for multi-tenant computing, addressing the security and isolation limitations of the traditional PMP mechanisms. This work presents the first open-source hardware implementation of the MPT draft specification (v0.4). Our design features a multi-level cache for accelerated permission checking and an L1TLB extension to reduce query frequency, with a decoupled architecture for portability. Evaluation shows only 2.32\% average SPEC06 performance overhead and a 0.244\% core area overhead, providing a hardware reference for SMMPT standardization.
Bio: Haoyuan Liu, a Digital Design Engineer at the Beijing Institute of Open Source Chip (BOSC), specializes in RISC-V security areas such as MPT, CFI, and PMP. He actively contributes to the XiangShan open-source RISC-V CPU.
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Heuristic-free system call interception on RISC-V
Blind submission #3EZXZV in Europa. On Tuesday 9, at 17h45.
Ottavio Monticelli, Iacopo Colonnelli, and Marco Edoardo Santimaria.
Abstract: Many applications benefit from the ability to intercept, block, or modify system calls efficiently. Binary rewriting is one of the fastest techniques to achieve this, but it often relies on instruction-dependent heuristics that limit its applicability. To date, exhaustive rewriting techniques (introduced by zpoline) are only available for x86-64 ISA. This work introduces vpoline, the first fully heuristics-free system call interception library for RISC-V. By leveraging the RISC-V linker relaxation mechanism, vpoline achieves the same benefits as zpoline while overcoming the intrinsic limitation of requiring privileged access.
Bio: Iacopo Colonnelli is an Assistant Professor in the Department of Computer Science at the University of Turin. He serves on the Technical Committee of the Common Workflow Language (CWL), and is a founding coordinator of the CWL4HPC working group. He has co-authored over 40 peer-reviewed publications in national and international journals and conferences, and has contributed to more than 10 funded research projects. He is currently the local Principal Investigator for the DARE European project (total budget: e240M). His research interests include workflow modeling and management in heterogeneous distributed architectures, high-performance computing and I/O, distributed confidential computing, and large-scale data science.
Bio: Marco Edoardo Santimaria is a Ph.D. student in Modeling and Data Science at the University of Turin, where I focus on developing methods and tools to optimize the performance of file-based scientific workflows. His research centers on the CAPIO methodology (born out of a collaboration between the University of Turin and the University of Pisa), which consists of two main components: the CAPIO middleware, a scientific tool designed to enhance I/O performance by enabling transparent streaming capabilities and providing a distributed, in-memory file system without requiring modifications to the workflow’s source code—and CAPIO-CL, a coordination language developed to express file dependencies and annotate streaming semantics across workflow steps.
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Wednesday 10
Keynotes
Details
Keynotes
Talks
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Invited talks
Panels
Invited talks
Talks
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Details
Details
RISC-V State of the Union
Keynote in Europa. On Wednesday 10, at 09h00.
Krste Asanović.
Abstract: In this session RISC-V’s Chief Architect will give an overview of RISC-V adoption across computing markets from Embedded to AI. Krste will discuss new developments in the RISC-V ISA, including security extensions and matrix extensions for AI, as well as new profile and platform initiatives.
Bio: Krste Asanović is Professor Emeritus and a Professor of the Graduate School in the EECS Department at UC Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998, then joined the faculty at MIT, receiving tenure in 2005. He returned to Berkeley in 2007, where he co-founded the Berkeley Parallel Computing Laboratory, led the ASPIRE Lab, and co-led the ADEPT Lab and Berkeley SLICE Lab. His main research areas are computer architecture, VLSI design, parallel programming, and operating system design. He has led the RISC-V open ISA project at Berkeley from its inception in 2010 and co-founded the RISC-V Foundation in 2015, which has now become RISC-V International, where he serves as Chief Architect. He also co-founded SiFive in 2015 to commercialize RISC-V processors, serving as Chief Architect there. He is an ACM Fellow and an IEEE Fellow.
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Nuclei: Full-Spectrum RISC-V IP & Automated SoC Design from Months to Hours
Keynote in Europa. On Wednesday 10, at 09h30.
Bob Hu.
Abstract: This presentation introduces Nuclei’s Subsystem Architector, a game-changing automation tool for RISC-V SoC design. As a leading Chinese RISC-V IP vendor, Nuclei delivers a full lineup of self-developed cores from M0-class ultra-low-power to A78-class high-performance processors, plus a complete SoC IP portfolio. Featuring an intuitive GUI, the tool enables end-to-end subsystem configuration, auto-verification, and one-click generation of production-ready deliverables. It cuts design/verification efforts by up to 95%, slashing iteration time from months to hours. Proven in IoT, industrial, automotive and multimedia projects, it empowers efficient, differentiated SoC development.
Bio: Founder & Chairman of Nuclei System Technology. RISC-V pioneer in China; author of best-selling RISC-V Chinese book. Ex-Marvell/Synopsys CPU design expert (15+ years). Founded Nuclei (at 2018) to deliver full-spectrum RISC-V IP and automated SoC design solutions, empowering global designers with revolutionary technology.
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ARBEL™ The Leading Server-Class RISC-V CPU
Keynote in Europa. On Wednesday 10, at 09h45.
Yiftach Gilad.
Abstract: Yiftach will introduce NextSilicon’s Arbel program, which includes a few generations of RISC-V out-of-order super scalar core systems, including a silicon chip and mini computer, and the plans for the first RISC-V server-grade high-performance RISC-V CPU.
Bio: Yiftach Gilad is the Senior Director of RISC-V CPU at NextSilicon, where he leads the development of advanced processor architectures designed for the next generation of AI and high-performance computing systems. With deep expertise in CPU microarchitecture, system design, and silicon development, Yiftach plays a central role in shaping the company’s RISC-V strategy and the evolution of the Arbel processor. Yiftach has over 20 years of experience in engineering, having worked at Intel for 18 years, until 2021, when he joined NextSilicon. There, he has been instrumental in transforming ambitious architectural ideas into real, production-ready silicon.
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RISC-V: Enabling Open Physical AI
Keynote in Europa. On Wednesday 10, at 10h00.
Luca Benini.
Abstract: Autonomous systems’ (robots, cars, satellites…) capabilities will be driven by Physical AI, Energy efficiency is not the only key constraint for future physical AI chips, as safety and robustness are extremely critical for autonomous operation To tackle the compound challenge, we need to aggressively optimize efficiency, leveraging specialization across all levels of the chip design hierarchy, pushing into domain-specific design automation tools and methodologies, while at the same time accounting for the increasing reliability concerns in advanced IC technology. In this talk, I will give concrete examples of how RISC-V enables deep domain specialization, for efficient and safe, reliable Physical AI, emphasizing the strategic importance of an open-platform approach.
Bio: Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Università di Bologna. He received a PhD from Stanford University. He is a Fellow of the IEEE, of the ACM, a member of the Academia Europaea and a funding member of the Italian Academy of Engineering and Technology. He is the recipient of various awards, including the 2023 IEEE CS E.J. McCluskey Award, and the 2024 IEEE CS Open Source Hardware contribution Award.
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Utilizing the RISC V Architecture to Accelerate Real Time Motor Control Applications
in Demo Theater. On Wednesday 10, at 10h35.
Sean Murphy.
Abstract: In this talk, I will present a novel approach for accelerating real-time motor control applications using a MIPS defined trigonometric math custom instruction extension on RISC V. One of the most widely used algorithms in motor control is Field Oriented Control (FOC). Within the FOC loop, the Park and Inverse Park transformations require repeated sine and cosine computations, which can be a significant performance bottleneck in software-based implementations. I will walk through a simple software implementation of the FOC loop and demonstrate the minimal code changes required to take advantage of custom trigonometric instructions. By offloading these operations to dedicated execution units integrated directly into the CPU pipeline, the solution delivers substantial performance improvements at the algorithm and system level while maintaining a software-friendly programming model. The talk will also discuss why tightly integrated custom execution units can provide better performance, power efficiency, and area utilization compared to traditional accelerators or heterogeneous compute approaches. Using RISC V custom instructions, software developers can access application-specific hardware acceleration with minimal complexity and without rewriting core algorithms. I will conclude by showing how accelerating motor control algorithms enables more precise, faster, lighter, and more efficient motors—benefiting applications in robotics, industrial automation, electric vehicles, and emerging real-time AI systems.
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VASCO: ASIC Test Platform for Hardware Security on FD-SOI
in Demo Theater. On Wednesday 10, at 10h45.
Stefano Di Matteo.
Abstract: As cybersecurity threats continue to evolve, hardware security has become a critical issue in the design of electronic devices. The advent of quantum computing has forced standardization bodies to rethink cryptographic foundations, leading to the rise of Post-Quantum Cryptography (PQC) as a strategic priority. At the same time, the RISC-V open-source instruction set architecture is emerging as a key enabler of secure hardware, offering new opportunities to design intrinsically secure microarchitectures. To address these research opportunities, CEA has developed VASCO, an ASIC platform designed to innovate, implement and characterize secure hardware primitives. It supports the development of robust countermeasures against side-channel attacks, fault injection and other physical security threats. In addition, VASCO Is adopted for characterization of security primitives such as True Random Numbers Generators (TRNGs) and Physically Unclonable Functions (PUFs). VASCO focuses also on PQC, which requires specialized hardware accelerators to achieve efficient and secure implementations. This demo will present the latest advancements made with VASCO#3, which was fabricated in 2025.
Bio: Stefano Di Matteo received his M.Sc. (2019) and Ph.D. (2023) respectively in Electronic Engineering and Information Engineering from the University of Pisa. He is currently a tenure-track researcher in hardware implementation of Post-Quantum Cryptography at CEA in Grenoble. His research interests include hardware implementation of PQC with countermeasures against physical attacks, RISC-V architectures, and Instruction Set Extensions for PQC
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DiffTest-H: FPGA-Accelerated RISC-V Co-simulation Verification Beyond 10 MHz
in Demo Theater. On Wednesday 10, at 10h55.
XU AN and Yinan Xu.
Abstract: Verification has become one of the most time-consuming stages in modern high-performance processor development. Co-simulation compares the Design Under Test (DUT) against a reference model (REF) at instruction granularity, providing strong debuggability, but existing software-based solutions are limited to KHz-level speeds and cannot meet industrial-scale verification demands. FPGA platforms can accelerate processor simulation to tens of MHz; however, massive and frequent hardware-software communication between the FPGA-hosted DUT and software REF still constrains co-simulation throughput. We present DiffTest-H, an FPGA-accelerated co-simulation framework for industrial-scale RISC-V processor verification. By exploiting the structural, ordering, and behavioral characteristics of verification data, DiffTest-H optimizes communication through compression and packaging while preserving instruction-level comparison and debugging capability. It reduces communication overhead by up to 99.7% with 3.2% additional area overhead on Xilinx VU19P, achieving co-simulation speeds beyond 10 MHz and enabling faster verification iteration. DiffTest-H has been deployed to verify XiangShan, a high-performance out-of-order RISC-V processor, covering interrupts, memory hierarchy behaviors, vector extensions, and virtualization. Across FPGA and emulator platforms, it has helped uncover more than 151 complex bugs in XiangShan, demonstrating its effectiveness for large-scale industrial processor verification.
Bio: Yinan Xu is an Assistant Professor at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). He received his B.Eng. degree from the University of Chinese Academy of Sciences in 2019 and his Ph.D. degree from ICT, CAS in 2025. He is a core developer of the XiangShan open-source high-performance RISC-V processor, where he has pioneered several agile design and verification techniques that have been successfully integrated into the project. His work has been recognized with the CAS President’s Special Award, the ICT Director’s Special Award (Xia Peisu Award), and the National Scholarship. His research contributions have been published in leading venues such as MICRO, HPCA, DAC, and JCST. Notably, XiangShan and its agile design methodology were selected as one of 2022 IEEE Micro Top Picks, recognizing it as one of the year’s most influential conference papers to computer architecture.
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From Eyewear to Silicon: RISC-V for Low-Power AI in Next-Generation Smart Glasses
Keynote in Europa. On Wednesday 10, at 11h30.
Marco Fariselli.
Abstract: Smart glasses must run multiple demanding applications—speech enhancement, eye tracking, and automatic speech recognition—simultaneously within tens of milliwatts of power budget. This poses a significant challenge for platforms constrained by milliampere-hour batteries and gram-scale form factors. Open hardware ecosystems, and RISC-V in particular, have proven invaluable. Rather than a contribution target, RISC-V provides a foundation to build on. Recent industrial and academic efforts have produced rigorously validated, ultra-low-power microarchitectures and extensive open knowledge that significantly lowers the barrier to custom silicon for teams whose expertise lies outside traditional semiconductor IP development. The second key challenge is on-device ML inference in a field where model architectures evolve faster than fixed-function accelerators. Hyper-specialized NPUs risk obsolescence before shipping. The solution is heterogeneous SoCs: systems where dedicated NPUs handle heavy-lifting for characterized inference workloads, tightly coupled with programmable RISC-V cores for pre/post processing and new operations. Crucially, RISC-V cores are extensible. Their ISA can be extended with custom instructions to efficiently cover emerging operators without full hardware redesigns—avoiding the obsolescence problem entirely. This talk offers a high-level perspective on how a product-driven company approaches custom silicon for smart eyewear, and why RISC-V sits at the center of that strategy.
Bio: After completing his Master’s degree in Electronic Engineering at the University of Bologna in 2019, Marco Fariselli began his career at GreenWaves Technologies, a fabless semiconductor company developing RISC‑V multicore processors to enable AI on ultra‑low‑power platforms. His work focused on bridging algorithm design and hardware execution, enabling neural networks and signal‑processing workloads to run efficiently on battery‑powered devices. He is currently with Luxottica, where he advances embedded machine learning deployment and contributes to the co‑design of next‑generation AI accelerators. His interests lie at the intersection of software optimization, hardware‑aware machine learning, and scalable edge intelligence on emerging architectures such as RISC‑V.
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RVEdge-Vision: A Fully Open, Ultra-Efficient On-Device AI Platform for Smart Eyewear
Non-blind submission #UCYLJC in Europa. On Wednesday 10, at 12h00.
Michele Magno.
Abstract: Smart eyewear promises unobtrusive, context-aware human–computer interaction by leveraging strategically placed multimodal sensors and on-device intelligence. However, integrating high-bandwidth sensing and machine learning inference within a compact and lightweight form factor remains challenging due to strict constraints in power consumption, memory footprint, and computational efficiency.This work presents RVEdge-Vision, an open hardware and software platform built on the RISC-V ecosystem that enables rapid prototyping and evaluation of next-generation smart glasses. The platform adopts a modular architecture supporting both frame-based and event-based vision sensors. To the best of our knowledge, this is the first open smart-glasses platform integrating event-based vision sensing in a glasses form factor, enabling ultra-efficient visual perception for wearable edge AI systems. The system incorporates a hardware–software co-designed power management framework optimized for battery-operated edge devices and continuous sensing workloads. As a reference implementation, we present a compact smart-glasses prototype that integrates multimodal sensing and on-device ML acceleration. The device can operate for several hours on a 300 mAh battery while sustaining real-time embedded vision workloads. A YOLOv8-based hand gesture recognition runs on-board with a few ms latency without relying on cloud connectivity. By releasing the platform as open hardware, OpenEdge RV aims to accelerate innovation within the RISC-V and open-edge AI communities, providing a reproducible foundation for research in wearable sensing, neuromorphic vision, and ultra-efficient on-device intelligence.
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RIVIERA: A Programmable RISC V Edge Architecture for NFC Signal Processing
Blind submission #HC7JS8 in Europa. On Wednesday 10, at 12h15.
Luca Lingardo.
Abstract: RIVIERA core, developed within Chips-JU TRISTAN Project, is a valid alternative to State-of-Art DSP architectures used in NFC Readers downlink signal processing. Instead of relying on custom hardware, RIVIERA employs an open source RISC-V core and its ISA extension interface to implement a software defined-radio (SDR) architecture, thus moving processing to the extreme edge of an NFC communication system. The first RIVIERA prototype targets decoding of NFC Type A tags responses and is ready by-design to cover other NFC standards and rates. By replacing hardened logic functions with SW data processing supported by a general-purpose DSP accelerator, RIVIERA reduces pre-silicon engineering effort, enables continuous post silicon improvements, and facilitates portability across SoCs designs and technology nodes. This work demonstrates how application-specific custom RISC V ISA extensions can effectively and efficiently handle RF baseband workloads, paving the way for the adoption of SDR architectures in RF communications for the IoT mass market.
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Accelerating RISC-V Innovation with open MPACT Tools from Google
Non-blind submission #JKTENR in Europa. On Wednesday 10, at 12h30.
Tor Jeremiassen and Yenkai Wang.
Abstract: The MPACT Tools portfolio provides open-source tools that increase the velocity of HW-SW co-design and development of RISC-V based systems. MPACT-Sim [1] is an ISS framework in C++ that makes it easier to create ISSs from scratch, and supports rapid changes in response to ISA design changes or user-needed functional enhancements. Using DSLs to describe the instruction set and encoding, it automatically generates instruction decoder source, and provides support for generating assemblers and disassemblers. MPACT-Sim enables rapid HW/SW co-design and early pre-Silicon software development. MPACT-RiscV [2] (built using MPACT-Sim) is a highly configurable RiscV ISS, with an interactive command interface for assembly level debugging and a customizable assembler which generates both relocatable and executable output files. To demonstrate the practical impact of the MPACT ecosystem, we present the real-world case study of the CoralNPU machine learning core [3], which is focused on development and execution of ML kernels. The CoralNPU-MPACT ISS [4] development was significantly accelerated by leveraging the fundamental MPACT-Sim and MPACT-RiscV infrastructure, requiring only limited modifications to support the additions to the CoralNPU’s instruction set and memory access rules. The CoralNPU UVM testbench [5] captures every retired instruction via the standardized RISC-V Verification Interface (RVVI) and steps the MPACT ISS model using a SystemVerilog DPI bridge. The testbench then retrieves golden reference values from the model to verify equivalence against the CoralNPU RTL, detecting functional bugs during development.
Bio: Tor Jeremiassen is a senior staff software engineer at Google LLC working on tools supporting architectural exploration, in particular, instruction level simulation frameworks. He brings with him 30 years of experience in writing simulators and frameworks for a variety of processors and application specific accelerators, particularly in the embedded space. Tor earned a Ph.D. in Computer Science from the University of Washington, specializing in compile time optimizations to improve cache performance on shared memory multiprocessors. Tor also holds an M.S. in Computer Science from the University of Washington, and a B.S in Computer Science from the University of Texas at Austin.
Bio: Yenkai Wang is a Senior Software Engineer at Google working on RISC-V architectural validation and system simulation. His professional experience is in the areas of HW/SW co-design, system verification, FPGA validation, and performance modeling. Yenkai earned a Master of Computer Science from the University of California, Irvine. He also holds an M.S. in Computer Engineering from National Yang Ming Chiao Tung University.
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SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification
Blind submission #QVKCU9 in Europa. On Wednesday 10, at 12h45.
Yinan Xu.
Abstract: The growing complexity of RISC-V processors, driven by rapidly expanding ISA extensions and sophisticated microarchitectures, has made functional verification a dominant bottleneck. Contemporary CPU verification commonly relies on RTL co-simulation against a software reference model, but on hardware-assisted simulation platforms (e.g., FPGAs) this workflow is fundamentally limited by high-volume communication between the accelerated RTL and the host-executed reference, preventing verification throughput from scaling. This paper addresses this by eliminating the RTL-host interaction bottleneck and proposing a Synthesizable Verification Methodology (SVM). We re-architect a RISC-V reference model as synthesizable hardware and deploy it alongside the design under test on the same acceleration platform, enabling fully hardware-based co-simulation at near-native speeds (60 MHz on FPGAs) while preserving reference-model checking and debug observability.
Bio: Yinan Xu is an Assistant Professor at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). He received his B.Eng. degree from the University of Chinese Academy of Sciences in 2019 and his Ph.D. degree from ICT, CAS in 2025. He is a core developer of the XiangShan open-source high-performance RISC-V processor, where he has pioneered several agile design and verification techniques that have been successfully integrated into the project. His work has been recognized with the CAS President’s Special Award, the ICT Director’s Special Award (Xia Peisu Award), and the National Scholarship. His research contributions have been published in leading venues such as MICRO, HPCA, DAC, and JCST. Notably, XiangShan and its agile design methodology were selected as one of 2022 IEEE Micro Top Picks, recognizing it as one of the year’s most influential conference papers to computer architecture.
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“PRG32: Teaching RISC-V Through Playable Game Cartridges"
in Demo Theater. On Wednesday 10, at 13h15.
Raffele Montella.
Abstract: PRG32 is an open-source educational platform that teaches RISC-V programming by developing playable 32-bit game cartridges. Inspired by retro-gaming consoles, PRG32 allows students to write small games in RISC-V assembly or C, package them as .prg32 cartridges, and run them on a lightweight runtime targeting RISC-V hardware and emulated environments. The demo presents the complete PRG32 workflow: writing a simple game, building the cartridge, loading it into the runtime, and executing it as an interactive program with graphics, input, and game logic. By turning low-level programming concepts into tangible, playable outcomes, PRG32 helps students understand registers, memory, control flow, graphics buffers, input handling, compilation, and system interfaces in a practical, engaging way. The platform is designed for computer architecture, systems programming, and introductory embedded computing courses. It supports both assembly-first and C-based teaching paths, enabling instructors to connect abstract RISC-V concepts with hands-on experimentation. The demo will show how PRG32 can be used in the classroom to make RISC-V programming more accessible, motivating, and fun.
Bio: Raffaele Montella is an Associate Professor with tenure in Computer Science at the Department of Science and Technologies (DiST), University of Naples “Parthenope” (UNP), Italy.
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High performance RISC-V Image Processing Chip EAI8800
in Demo Theater. On Wednesday 10, at 13h25.
Changqing Li.
Abstract: The EAI8800 is an automotive-grade high-performance dedicated chip for CMS electronic mirrors built on the RISC-V CPU developed by ESWIN Computing. Adopting a heterogeneous multi-core RISC-V CPU consisting of two large cores and one small core, ESWIN computing self-developed ISP and tightly-coupled video processing architecture. This single chip realizes the full-link workflow of collection, processing and display, addressing the pain points of traditional general-purpose chips such as high latency, high power consumption and high costs. It boasts outstanding core performances: the camera-to-panel latency is no more than 16.6ms with power consumption below 500mw. It supports 1920×1080@60FPS as well as HDR and night vision enhancement, conforms to ASIL-B functional safety standards.
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Matrix Extensions for RISC-V: Delivering on the Promise
Invited talk in Europa. On Wednesday 10, at 14h30.
Dr. Philipp Tomsich.
Abstract: When the RISC-V matrix extensions effort was restructured into four complementary approaches at Summit Europe 2025 in Paris, it was a bold architectural bet — that the breadth of the RISC-V ecosystem demands not one rigid solution but a family of extensions spanning from lightweight vector-matrix primitives to fully independent matrix engines. One year later, that bet is paying off. This talk reports on the rapid progress across the matrix extension family as two of the four extensions — the Integrated Matrix Extensions (IME) and the Vector Matrix Extensions (VME) — converge on specification freeze. We trace the architectural decisions that brought IME and VME from concept to maturity: algebraic tile geometry that scales naturally with VLEN, the deliberate reuse of RVV state for seamless software integration, and the introduction of dedicated accumulator registers to unlock higher computational intensity where implementations demand it. Crucially, work is starting to unify IME and VME through a common LLVM-MLIR lowering path — giving compilers and AI/ML frameworks a single abstraction that targets both extensions, ensuring that the software ecosystem scales with the hardware rather than fragmenting across it. For Europe’s semiconductor industry — from research institutions and startups to established design houses — standardized, open matrix extensions represent a strategic opportunity: competitive AI/ML and HPC capability on an open ISA, free from proprietary lock-in. RISC-V matrix support is no longer a roadmap item. It is arriving.
Bio: Dr. Philipp Tomsich is Chief Technologist and Founder of VRULL GmbH, providing strategic R&D for semiconductor companies. He chairs the RISC-V Applications & Tools Committee, serves on the RISC-V Board of Directors, and is Vice-Chair of the Technical Steering Committee, where he champions software ecosystem growth and standards alignment, including efforts to publish RISC-V under ISO. He instigated the standards-development matrix operations and AI/ML, serving as principal editor of the Integrated Matrix Extension and as the Vice-chair of the Attached Matrix TG.
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Realising the Future of European Computing from Research to Industry
Panel in Europa. On Wednesday 10, at 14h45.
Abstract: Europe has been a key contributor to the development of modern computing, inventing fundamental hardware and software technologies, and growing highly successful companies with worldwide reach. But in a new era of AI and Cloud computing, how can Europe redefine its approach and put itself at the forefront of computing innovation and success?
This panel will debate the European approach to computing and how RISC-V can be a powerful tool for delivering an innovative, successful, and uniquely European vision of the future of computing.
What is the vision of European computing sovereignty, and to what extent is this becoming reality? What is the role of the policy makers on the European strategy and the relative influence of European organizations, national entities and venture capitals/investors? What are the main differences between the US, Asia, and Europe in terms of sustainability of the industrial ecosystem? How do the laws and rules of Europe influence our success? What are the technologies and applications Europe needs to deliver? Where are its strengths and high potential application spaces? How can we close the gap regarding maximizing the technology transfer between research/academia to industry? How can we train the highly skilled workers needed? What is the balance between addressing domestic needs and an international market?
Moderator: Florian Wolhrab - Open Hardware Foundation
Panelists: Georgi Kuzmanov - Chips-JU Sachiko Muto - Open Forum Europe Enrico Sangiorgi - Chips-IT Edward Wilford - OMDIA Fabien Piuzzi - Scaleway
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Transforming MCUs in an AI-Defined Era
Invited talk in Europa. On Wednesday 10, at 16h30.
Edward Wilford.
Abstract: As artificial intelligence reshapes embedded systems, MCUs are evolving from simple control devices into intelligent, distributed computing nodes. This talk explores how RISC-V architecture and scalable AI frameworks are enabling a pragmatic, incremental approach to system transformation—particularly critical in automotive applications where safety, reliability, and legacy integration remain paramount.
Bio: Edward is the Senior Research Director, Automotive, having previously covered automotive AI and semiconductors as Senior Principal Analyst, IoT, at Omdia. He has written extensively on embedded applications processors and GPUs, edge AI, advanced connectivity, and novel semiconductor architectures such as RISC-V. He started in the industry in 2016 when he joined Arm as a market intelligence analyst, leading market research and forecasting in the automotive and IoT division. He has also worked in financial services and media roles in London. He has a BA from Durham University and an MPhil in Linguistics from the University of Cambridge.
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Ultra Low Power RISC-V core: Retention with Warm Restart Extension
Blind submission #G7YSXG in Europa. On Wednesday 10, at 16h45.
Anne Merlande.
Abstract: Energy saving is a top priority for STMicroelectronics products. For the STxP5 embedded CPU based on the RISC-V architecture, there is a particular focus on minimizing static power when the core is inactive. Additionally, it is important to optimize the CPU restart time, silicon area, implementation complexity, and software overhead. The Ultra Low Power Retention with Warm Restart Mode addresses these challenges by maximizing power savings and reducing drawbacks typically associated with resuming operation. This solution leverages the modular, scalable, customizable, and extensible nature of the RISC-V architecture by defining and implementing a custom RISC-V extension and tailored microarchitecture.
Bio: Anne Merlande is a processor architect at STMicroelectronics in Grenoble, within the Computing and Compilers Center. As Senior Member of Technical Staff, her expertise field covers processor and system architecture, CPU microarchitecture and frontend design, low power and energy efficient subsystems, security and functional safety. She graduated from Institut Supérieur d’Électronique de Paris in 1995 and joined STMicroelectronics in 1999, after four years as an ASIP designer at Matra. At STMicroelectronics, she has led the design of the ST200 processor families, acted as technical lead for ARM Cortex A subsystem frontend design, and led top level integration for automotive SoCs. She currently works as Processor Architect on the STxP5 core family, with a particular focus on ultra low power operation, security, and functional safety.
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RISC-V Custom Instructions for Automotive Control and DSP Algorithms Compliant with ISO 26262
Non-blind submission #8LUM7U in Europa. On Wednesday 10, at 17h00.
Andreas Mauderer and Zdenek Prikryl.
Abstract: The stringent safety requirements of the automotive industry necessitate compliance with standards like ISO 26262. Processor cores, often pre-certified to ASIL-B or ASIL-D, face certification risks when modified. This work focuses on the development of custom instructions that are integrated through Codasip’s Bounded Customization (BC) without directly modifying the core’s verified RTL. The paper details a workflow for this process and presents performance results demonstrating the acceleration achieved for key automotive and DSP algorithms, including Field Oriented Control (FOC). All extensions were consolidated into a unified custom processor, termed as the Motor Control with DSP (MCXD) core, featuring a scheduling algorithm that coordinates FOC and filtering routines. Synthesis showed an area increase of ~31%, while runtime and instruction count measurements demonstrated performance improvement of up to ~21%. These results validate that domain-specific acceleration can be achieved within the boundaries of ISO 26262.
Bio: Andreas Mauderer received the diploma degree in computer science from the University of Karlsruhe, Germany, in 2009. He received his PhD in computer science at the University of Tuebingen in 2014. He is working at Bosch since 2009 in the business unit Mobility Electronics in the field of Virtual Prototyping and on-chip processors for automotive ICs. Furthermore, he is active in various publicly funded projects regarding these topics.
Bio: Zdenek received the PhD degree from the Brno University of Technology, Czechia, where he played a significant role in the research related to processor development automation. It enabled the creation of the processor development tools, Codasip Studio, that he has been driving ever since at Codasip. Zdenek has continued working as the chief architect of Codasip Studio for more than 12 years. He has also been the architect of diverse processor cores, including but not limited to 16/32-bit architectures for IoT, 32/64bit DSP-oriented architectures, or Linux capable architectures. All of these architectures were developed using Codasip Studio, and many of them were based on the RISC-V ISA. Zdenek has been also involved in embedded systems design (software and hardware) and driving R&D activities for many years.
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Proposal of State Sensitive Counter (Sssscnt)
Non-blind submission #WWT8EV in Europa. On Wednesday 10, at 17h15.
Fengxue Zhang and Bohua Kou.
Abstract: PELT (Per-Entity Load Tracking) is an exponential decay-based per-entity load tracking algorithm in the Linux kernel. It significantly enhances the scheduler’s load awareness accuracy, response latency, and energy efficiency. However, there are still drawbacks in load tracking: The load metrics that are used are not CPU-frequency invariant. The advent of CPU frequency scaling causes task physical runtime to fluctuate with frequency, which, if uncorrected, distorts util_avg and leads to scheduling misjudgments. To address this, the kernel employs hardware counters (e.g., Intel APERF/MPERF, ARMv8.4-AMU) to implement frequency invariance accounting, ensuring util_avg remains anchored to the CPU’s maximum capacity, thereby maintaining load statistics accuracy and scheduling optimality in dynamic frequency environments. Targeting RISC-V architectures, this proposal introduces State sensitive Counters to fill the gap in PELT frequency invariance support. Together, these counters enable the derivation of real-time operating frequency and normalized utilization without costly synchronous queries.
Bio: (Fengxue Zhang). As a senior Engineer in the Firmware Team at Alibaba Damo Academy, Esther specializes in system and power management software standards, with a focus on architecting and developing power management frameworks across diverse operating systems (OS) and firmware technologies. Her work drives innovation in energy-efficient computing and system optimization, aligning with industry-leading specifications to enhance hardware-software synergy.
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Enabling High-Performance Storage for RISC-V: Porting the Lustre Parallel File System
Non-blind submission #RRD8XA in Europa. On Wednesday 10, at 17h30.
Dave Cremins.
Abstract: Lustre powers approximately 70% of TOP500 supercomputers and is essential infrastructure for high-performance computing (HPC). Our work enables RISC-V systems to access Lustre storage clusters, addressing a critical gap in the RISC-V HPC ecosystem. The port required only 8 minimal patches (19 lines changed across 9 files) to Lustre 2.17.0, demonstrating the maturity of both the RISC-V Linux ecosystem and Lustre’s portable codebase. We validated functionality through QEMU-based testing with multi-client mount operations, FIO, and IOR benchmarks. The patches are being submitted upstream to the Lustre project for inclusion in future releases.
Bio: Dave Cremins is a Principal Cloud Software Engineer at OPENCHIP, where he specializes in designing and building advanced cloud‑native systems at scale. With deep expertise in distributed architectures, automation, and infrastructure engineering, Dave plays a key role in shaping technical strategy and delivering high‑impact engineering solutions across the organization.
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An Open-Source CVA6S+ based High-Performance, Cache-Coherent Cluster for 64b Automotive MPUs
Blind submission #R7MK7D in Europa. On Wednesday 10, at 17h45.
Riccardo Tedeschi.
Abstract: Driven by the need for zonal control architectures in software-defined vehicles, open-source RISC-V cores are becoming a compelling solution for automotive microprocessor units (MPUs). We introduce a 64b cache-coherent, tightly coupled cluster built upon the industry-backed OpenHW CVA6S+ core and HPDCache, capable of executing SMP Linux and RTOS kernels. A design space exploration of the core branch predictor identifies an embedded tournament configuration that reduces its area by 11.6% with no loss in accuracy. Evaluated on the Splash-3 benchmark suite, the cluster achieves a geometric mean speedup of 1.75× over a single-core baseline, and a 1.21× speedup over a prior implementation based on the scalar CVA6 and legacy cache subsystem. Synthesized in GlobalFoundries’ 12 nm FinFET, the dual-core cluster incurs less than 1% per-core area overhead, with the coherent unit in the interconnect contributing only 35 kGE (1.5%) to the total cluster footprint.
Bio: Riccardo Tedeschi received his Master’s Degree in Electronic Engineering from the University of Bologna in 2023. He is now pursuing a Ph.D. in Digital Systems Design within the Department of Electrical and Information Engineering (DEI) at the same university and is currently a visiting researcher at ETH Zürich. His research centers on RISC-V architectures tailored for embedded platforms, particularly in the areas of performance optimization and reliability.
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Thursday 11
Keynotes
Talks
Keynotes
Talks
Details
Invited talks
Panels
Details
Talks
Events
Developing an Open Agentic SoC
Keynote in Europa. On Thusrday 11, at 09h00.
Tanya Dadasheva.
Abstract: Ainekko’s Agentic SoC is an open, full-stack approach to AI-native silicon that treats hardware as a programmable, composable substrate for model execution rather than a fixed target. Built on a many-core RISC-V architecture with tile-based compute and memory, the platform enables automated model-to-hardware mapping, dynamic quantization, and workload-specific system composition at packaging time, eliminating the need for per-model tape-outs. We invert the traditional stack: models define the hardware. Our approach sits between FPGA flexibility and etching models into ASIC-level efficiency, delivering high performance and practical economics while remaining fully programmable to adapt to rapidly evolving models and architectures. Our programmable RISC-V fabric has been validated with a 1,088-core tape-out and is designed to scale to 4,000+ cores. On top of this foundation, we have built a set of open building blocks across RTL, compiler, and runtime, which we are open-sourcing through the OpenHW Foundation (CORE-ET project) and AIFoundry. This open ecosystem enables developers, researchers, and AI agents to co-design across the full stack and directly optimize execution on hardware. This openness is essential: supporting fast-moving models, heterogeneous edge workloads, and agent-driven development requires a system where new kernels, quantization strategies, and architectural innovations can be introduced and composed without vendor constraints.
Bio: Tanya is a co-founder of Ainekko: a 100% open-source company on a mission to democratize inference and fine-tuning of all popular open-weight models with a hardware/software product. Tanya also has started AIFoundry open source ecosystem of AI projects and engineers working on different building blocks of these stacks while maintaining the common goals and compatibility. Before that Tanya has been involved in the tech world and open source in many different roles. She is an ex-VC @Almaz Capital with OSS and RISC-V portfolio, ex-OSS policy maker, working to integrate developing countries into the global scene while building local independent infrastructure, founder of project helping tech companies affected by the wars to leverage OSS for freedom of tech from politics.
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RISC-V for the Planet: Open-Source Microprocessors in the Internet of Trees
Keynote in Europa. On Thusrday 11, at 09h30.
Marcelo Zuffo.
Abstract: Climate change and environmental degradation demand new approaches for large-scale, continuous, and intelligent sensing of natural ecosystems. The Internet of Trees proposes a distributed infrastructure where smart environmental probes deployed in forest environments become active nodes in a real-time environmental intelligence network—requiring computing platforms that are low-power, secure, adaptable, and affordable. RISC-V offers a powerful foundation for next-generation environmental sensing systems. As an open-source ISA, it enables technological flexibility, design transparency, and long-term digital sovereignty, while allowing customized processors tailored to edge AI, wireless sensor networks, secure communication, and ultra-low-power operation. These features are especially critical for climate-oriented deployments in remote, resource-constrained environments. This keynote presents the Internet of Trees as a case study for the strategic use of open-source microprocessor technology, discussing how RISC-V supports distributed sensing, local data processing, trusted operation, and scalable integration with cloud-based environmental platforms. Beyond technical efficiency, open microprocessor ecosystems can strengthen local innovation and sustainable semiconductor capacity—making RISC-V not merely a processor architecture, but an instrument for building resilient, sovereign infrastructures for planetary monitoring. The Internet of Trees illustrates how open silicon can connect sustainability, intelligence, and environmental stewardship, a perspective particularly relevant for emerging economies seeking both climate action and technological autonomy. The convergence of open hardware and environmental intelligence may define a new class of digital infrastructure for the living world. RISC-V can be one of its most important enabling technologies.
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World's first lunar exploration rover using FPGA-based RISC-V processor
Non-blind submission #MCBEUE in Europa. On Thusrday 11, at 10h00.
Tetsuo YOSHIMITSU.
Abstract: A small lunar rover named “LEV-1” made surface mobility exploration on the Moon in January 2024. This was the first lunar exploration robot in our country. LEV-1 was installed in the lunar lander “SLIM” and was deployed onto the Moon surface just before landing. LEV-1 explored over the landing area fully autonomously after the deployment. The obained data inclusing images were directly transmitted to the Ground with no relay by the lander. The onboard computer of the rover used a RISC-V soft-core CPU implemented within the FPGA. The system is one of the world’s first onboard computers using a RISC-V processor being operated on the Moon. This paper describes the configuration of the RISC-V controller installed on LEV-1 rover as well as the technical background for using RISC-V in space applications.
Bio: He is a professor at the Institute of Space and Astronautical Science (ISAS) of the Japan Aerospace Exploration Agency (JAXA). He is engaged in solar system exploration, particularly research on planetary exploration rovers for celestial surfaces. As principal investigator, he developed the MINERVA and MINERVA-II rovers for the asteroid sample return missions of the Hayabusa and Hayabusa2 spacecraft. He has also been involved in multiple lunar exploration missions, including the OMOTENASHI CubeSat and the SLIM landing mission. He served as principal investigator for the LEV-1 rover for the SLIM mission.
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A User-Friendly and AI-Ready Desktop for RISC-V: Bianbu LXQt
Non-blind submission #WHFNV3 in Europa. On Thusrday 11, at 10h15.
Xiaogang Fan.
Abstract: We present Bianbu LXQt, a user-oriented desktop environment for RISC-V platforms built on a deeply adapted LXQt software stack, optimized for real hardware such as SpacemiT’s K1 and K3 SoCs. Unlike straightforward ports that assume x86-like hardware standardization, this work addresses common RISC-V Linux challenges, including fragmented peripheral support and the absence of a unified hardware abstraction layer. SpacemiT’s CPUs integrate AI-oriented instruction extensions such as IME, enabling CPU-based inference without discrete GPUs or NPUs, requiring coordinated adaptation across the OS and AI frameworks. Preserving LXQt’s lightweight design, we redesigned the UI and interaction logic to improve responsiveness and visual consistency on resource-constrained RISC-V systems. Development was accelerated using AI-assisted tooling, while continuous feedback from educators and early adopters guided iterative fixes for lag, crashes, and complex configuration—letting users focus on creation, learning, and development rather than system tuning. The full software stack is open source with reproducible builds and modular components. We proved educational AI examples covering image recognition, speech processing, video analysis, and large language model inference, all with intuitive GUIs. Frameworks including ONNX Runtime, llama.cpp, and Ollama run reliably, demonstrating the feasibility of RISC-V systems for AI deployment and local AI development. Through practical system integration, community-driven iteration, and accessible AI tooling, this work shows RISC-V can deliver a polished, daily-driver desktop environment—moving beyond a demo into a trusted open platform for developers, educators, and innovators.
Bio: Senior Software Engineer at SpacemiT, specializing in system application development and customer support.
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Albania is an AI-Factory
Keynote in Europa. On Thusrday 11, at 11h30.
Kushtrim Shala.
Abstract: The European AI Factory initiative aims to distribute sovereign compute capacity across Europe, but participation from Western Balkans accession countries has remained largely aspirational. Albania is charting a different course. Albania’s ICT sector employs tens of thousands of skilled engineers, but almost entirely in software outsourcing—writing code for other countries’ products on other countries’ architectures. This model creates employment but not ownership, capability but not sovereignty. The age of AI demands transformation: from consuming compute to shaping it. This talk presents a strategy to establish one of Europe’s first RISC-V-native AI compute facilities. The initiative is designed not only to serve Albania’s public-sector AI needs but to act as a regional compute hub for the Western Balkans and a gateway for Middle Eastern partners seeking EU-aligned AI infrastructure. Critically, the strategy begins in the classroom. By embedding RISC-V into Albanian computer science and engineering education, the initiative connects that talent pipeline directly to a sovereign AI compute facility, transforming a generation of outsourcing engineers into architects of AI infrastructure. Kushtrim Shala draws on Albania’s track record in digital innovation to show how small, agile countries can move faster than larger member states in adopting open ISA infrastructure. The talk addresses what it takes to bootstrap a semiconductor culture and makes the case that RISC-V is not merely a technical choice but a strategic instrument of digital sovereignty—one that smaller nations can leverage to build resilient, independent AI capacity.
Bio: Kushtrim Shala is an Albanian technology entrepreneur, innovation strategist, and ecosystem builder with over 15 years of experience in ICT, digital transformation, and startup development. He holds a degree in Computing Sciences from the University of Tirana and an MBA from the University of New York Tirana. As Co-founder and Executive Director of ALBICT (Albanian ICT Association) and Co-founder of Digital Valley Albania (DiVA), an official European Digital Innovation Hub, Kushtrim has built bridges between technology, policy, and entrepreneurship across the Western Balkans. Under his leadership, ALBICT has supported more than 100 startups through eight accelerator cohorts. He is also co-founder of the Uplift Startup Accelerator, ICTSlab, and the Albanian ICT Awards. Recognized with the Golden Bee Award by the Prime Minister’s Office of Albania, he currently focuses on open hardware ecosystems, RISC-V, AI infrastructure, and digital sovereignty strategies for emerging European economies.
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All The Scaling, No New State: One Matrix ISA with Microarchitectural Freedom
Blind submission #ETWPMQ in Europa. On Thusrday 11, at 12h00.
Dr. Philipp Tomsich and Dr. Erich Focht.
Abstract: RISC-V’s Zvvm matrix extension stores all tile state in the standard V register file and derives tile geometry algebraically from VLEN, SEW, and a new aspect-ratio field λ. This yields arithmetic intensity that scales with VLEN: a binary compiled at VLEN=256 delivers higher throughput at VLEN=65536 with no recompilation. The same partial-VL mechanism that enables one-column-at-a-time embedded streaming also drives full HPC bulk tiling, while microscaling is integrated via vm-bit opcode aliasing with no new architectural state. Tile dimensions are not programmer-specified constants — they are consequences of existing parameters. The tile is always square: M = N = VLEN/(SEW×λ), with inner dimension K_eff = λ×W×LMUL. Arithmetic intensity (M/2) grows proportionally with VLEN, and the ratio of intensity to cache-to-VRF bandwidth remains constant — a provable algebraic identity with no equivalent in Arm SME or Intel AMX. Zvvm’s geometry knobs form an intent vocabulary expressed from both sides: software selects LMUL and VL to control K_eff depth and streaming granularity; hardware determines λ and VLEN to shape the tile for its datapath. Setting VL = K_eff with LMUL = 1 gives portable streaming; increasing LMUL or computing multiple C panels trades register pressure for compute intensity — all via the same opcode. Microscaling (MX) support is integrated by aliasing the vm bit in FP multiply-accumulate opcodes, introducing no new encoding space, registers, or modes.
Bio: Dr. Philipp Tomsich is Chief Technologist and Founder of VRULL GmbH, providing strategic R&D for semiconductor companies. He chairs the RISC-V Applications & Tools Committee, serves on the RISC-V Board of Directors, and is Vice-Chair of the Technical Steering Committee, where he champions software ecosystem growth and standards alignment, including efforts to publish RISC-V under ISO. He instigated the standards-development matrix operations and AI/ML, serving as principal editor of the Integrated Matrix Extension and as the Vice-chair of the Attached Matrix TG.
Bio: Dr. Erich Focht is a system architect and physicist currently working as a Senior Fellow at Openchip, where he leads the Accelerator-AI architecture group and focuses on the development of Artificial Intelligence (AI) and High-Performance Computing (HPC) accelerators. He holds a Ph.D. in theoretical physics from RWTH Aachen and has a professional background that spans computational physics, numeric algorithms, distributed systems software, parallel file systems and hardware-software co-design. Before his current role at Openchip, Erich spent over 25 years at NEC HPC Europe where he contributed to the system design of dozens of supercomputers, most of them present in the TOP500 list. Within the RISC-V open-source ecosystem, Dr. Focht contributes to the standardization of matrix operations as an active member of the IME TG, focusing on RISC-V matrix implementations. He also represents Openchip in the RVI Technical Steering Committee.
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ARCANE: Enabling High-Performance In-Cache Tensor Extensions in RISC-V
Blind submission #G7Y79Q in Europa. On Thusrday 11, at 12h15.
Flavia Guella and Vincenzo Petrolo.
Abstract: Modern data-centric workloads increasingly expose the limitations of traditional von Neumann architectures, where excessive data movement limits throughput and energy efficiency. While hardware accelerators improve performance, they often lack flexibility and still require costly memory transfers. Existing compute in- and near-memory solutions reduce the memory bottleneck but introduce usability challenges related to constraints on data placement. ARCANE is a cache architecture that doubles as a tightly-coupled near-memory coprocessor. The embedded RISC-V cache controller executes custom instructions offloaded by the host CPU relying on near-memory vector processing units within the cache memory subsystem. This architecture hides memory synchronization and data mapping from application software, while offering software-based Instruction Set Architecture extensibility. Evaluations demonstrate up to an 84x speedup on 8-bit convolution layers over a traditional system-on-chip, incurring only a 41.3\% area overhead.
Bio: Flavia Guella received the M.S. (with summa cum laude) in Electronics Engineering from Politecnico di Torino in 2023. She is currently pursuing the Ph.D. program in Electronics and Communications Engineering at Politecnico di Torino, under the supervision of Prof. Maurizio Martina and Prof. Guido Masera. Her research interests include RISC-V based in-cache computing, and co-design methodologies for the efficient deployment of neural networks on low-power systems.
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Evaluating Tenstorrent RISC-V Accelerators for High Performance Scientific Computing
Non-blind submission #HNQPKX in Europa. On Thusrday 11, at 12h30.
Elisabetta Boella.
Abstract: We implemented an N-body astrophysical simulation code and offloaded its most computationally intensive kernel to Tenstorrent RISC-V–based accelerators using the TT-Metalium programming interface. Performance was assessed on the Wormhole n300 card in terms of execution time and energy consumption, and compared with both an optimized CPU implementation and a CUDA version. The TT-Metalium implementation achieves a speedup of 2× over the CPU baseline, although its performance still slightly lags behind the CUDA implementation. Finally, we investigated strategies for scaling the application across multiple Tenstorrent accelerators, evaluating configurations with up to four devices.
Bio: Elisabetta Boella received her M.Sc. degree in Energy and Nuclear Engineering in 2009 from Politecnico di Torino (Turin, Italy) and her Ph.D. in Computational Plasma Physics in 2014 from the same institution. She currently works as HPC product specialist at E4 Computer Engineering (Scandiano, Italy), where she leads the company effort in several European projects, including MaX, SPACE and EoCoE. Her research interests include numerical modelling, parallel programming, and co-design practices. She has a long-time experience in the development and optimisation of parallel codes using the Message Passing Interface protocol. She is one of the main developers of the massively parallel plasma code ECsim. She also has extensive experience in Graphical Processing Unit (GPU) programming and off-loading of legacy codes to GPU.
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CHAKRA-GP: A Retargetable Compiler Framework for RISC-V GPGPU Architectures
Blind submission #FRDLL7 in Europa. On Thusrday 11, at 12h45.
Prachi Pandey and PRANOSE J EDAVOOR.
Abstract: The emergence of RISC-V as an open and extensible instruction set architecture has enabled the development of domain-specific accelerators and General-Purpose Graphics Processing Units (GPGPUs). While the RISC-V ISA provides support for scalar instructions and the RISC-V Vector Extension (RVV) enables data-parallel vector execution, these models do not directly support the Single-Instruction Multiple-Thread (SIMT) execution paradigm required by modern GPU architectures. Consequently, efficient software enablement for RISC-V–based GPUs requires compiler support capable of generating SIMT-oriented instruction sequences and managing massively parallel execution. This proposal talks about CHAKRA-GP, a hardware-optimized compiler framework for RISC-V–based GPGPU architectures. Built upon LLVM and MLIR infrastructures, CHAKRA-GP provides a scalable compilation pipeline enabling efficient kernel generation, memory optimization, and parallel execution mapping for massively parallel workloads. The compiler targets custom RISC-V GPGPU platforms and enables efficient execution of HPC, scientific computing, and AI workloads. The work demonstrates how an extensible compiler infrastructure can bridge the gap between the RISC-V ISA and SIMT-based GPU execution models, enabling efficient compilation for customizable RISC-V GPGPU architectures.
Bio: Ms. Prachi Pandey is a Senior Compiler Engineer at C-DAC, where she works on MLIR/LLVM-based compiler development for indigenous processors, GPUs, and AI accelerators. She has nearly two decades of experience in HPC, parallel programming, compilers, and runtime systems. Her research interests include compiler optimization techniques, automatic parallelizing compilers, performance portability for heterogeneous architectures, and parallelization strategies for HPC and AI workloads.
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RISC‑V at Scale: From Embedded Dominance to Application Processor Opportunities
Invited talk in Europa. On Thusrday 11, at 14h30.
John Holland.
Abstract: RISC‑V has emerged as one of the most important new architectures in decades, achieving widespread adoption in embedded systems and shipping at massive scale. But as the industry looks beyond embedded into application processors, a new set of challenges—and opportunities—comes into focus. This talk explores where RISC‑V stands today, what makes its next phase of growth fundamentally different, and why its future is likely to unfold unevenly across markets. It highlights key inflection points that will shape adoption and outlines where RISC‑V is poised to gain traction next.
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It's a RISC-V World: Innovation, Collaboration, Competition, and Deployment on a Global Stage
Panel in Europa. On Thusrday 11, at 14h45.
Abstract: The global nature of RISC-V is one of its greatest strengths. The RISC-V Instruction Set Architecture (ISA) is constantly developed and evolved by member organizations worldwide, with contributors working together on new features and capabilities across geographies and time zones. In turn, the RISC-V ISA provides the basis for the future of global computing innovation, addressing the diverse needs of countries, companies, educators and individuals.
In this session we bring together representatives of the RISC-V community from different continents to discuss the nature of a worldwide ecosystem. We will discuss the realities of RISC-V in different geographies: How the ISA drives innovation and solves specific local problems How RISC-V unlocks the potential of a global marketplace. The importance of digital sovereignty, and different approaches to research, education and training a new generation of engineers. Explore the tension between collaboration and competition. How are RISC-V members working together and supporting each other? Where does their location give them a competitive edge? Opportunities and challenges in cross-continent collaboration. Lessons learnt.
Join us to learn the global lessons of RISC-V deployment!
Moderator: Florian Wolhrab - Open Hardware Foundation
Panelists: P. Hari - C-DAC Teresa Cervero - Barcelona Supercomputing Center Marcelo Zuffo - University of Sao Paulo Jing Yang - Damo Academy
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A Proof-of-Concept RISC-V with 128-bit Extension
Blind submission #MUFY8Z in Europa. On Thusrday 11, at 16h30.
Frédéric Pétrot.
Abstract: Addressing ever-larger amounts of memory is a fact of (computerized) life. The authors of the RISC-V unpriviledge specification did recognize that and coined on less than one and a half page what could be a natural extension to 128-bit of the 32- and 64-bit RISC-V ISA. Given this RV128I draft, we (a) defined an ELF128 extension for binaries, (b) made gnu-based a cross-compilation environment able to use RV128I instructions and generate ELF128 binaries, (c) added support for this extension and ELF128 in QEMU, (d) added the necessary instructions and resources in the CVA6 processor.
Bio: Frédéric Pétrot got a Ph.D. in Computer Science in 1994, and the Habilitation in 2003, both at LIP6 lab, Université Pierre et Marie Curie, Paris, France. Since 2004, he is Professor at Grenoble INP - UGA/Ensimag, teaching mainly architecture and operating system classes. He joined the TIMA Lab, to work on various topics related to multiprocessor systems on chip. He is currently heading the joint UGA, Inria, CNRS team MADMAX.
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Accelerating Sparse Linear Solvers in OpenFOAM using RISC-V Vector Extensions
Blind submission #D3TVFS in Europa. On Thusrday 11, at 16h45.
Gabriele Ceccolini.
Abstract: Computational Fluid Dynamics (CFD) relies heavily on the efficiency of linear solvers based on sparse linear algebra kernels. Widely used frameworks like OpenFOAM exploit parallelism primarily at the domain decomposi-tion level via MPI. Support for vector/SIMD architectures is limited to compiler auto-vectorization. Furthermore, support for such architectures is limited by OpenFOAM’s internal matrix data format, which is intrinsically ill-suited for the contiguous memory accesses required for efficient execution on vector processors. In this work, we focused on two very different RISC-V architectures: the prototype long-vector EPAC accelerator and the commercial short-vector CPU Sophon SG2044. On these platforms, we optimized the Sparse Matrix-Vector multiplication (SpMV) using RISC-V vector intrinsics and integrated it into a custom smoother, performing a runtime conversion of internal data into a vector-friendly format. Experimental results on the EPAC test chip show a 6× speedup for the smoother; benchmarks on Monte Cimone (MCv2) cluster with the Sophon SG2044 processor achieve a 1.5× smoother speedup, proving that legacy CFD codes can be effectively accelerated on both research and commercial emerging hardware.
Bio: Gabriele Ceccolini received his Master’s degree in Computer Engineering from the University of Bologna in March 2026. He previously obtained his Bachelor’s degree from the same institution in 2023. Since May 2025, Gabriele has been collaborating with CINECA, focusing on the optimization of CFD algorithms on RISC-V platforms.
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Optimizing Llama.cpp and GGML for RISC-V Vector (RVV)
Non-blind submission #TX9SGW in Europa. On Thusrday 11, at 17h00.
Taimur Ahmad, Adeel Ahmad, Ahsan Jalil, and Ahsan Jalil.
Abstract: Llama.cpp is a widely used open-source platform for running Large Language Models (LLMs) on CPUs, but its support for RISC-V remains limited compared to x86 and ARM. Many floating-point and quantized kernels lack RISC-V Vector (RVV) implementations, restricting the performance of existing hardware. This work improves the upstream RISC-V performance by vectorizing core floating-point kernels and extending support across multiple quantization types, enabling first-class support for RVV in Llama.cpp. VLEN-aware data repacking is introduced to accelerate GEMM and GEMV kernels for both floating point and quantization types. The optimized kernels are validated across VLENs up to 1024-bit, with benchmarking on Banana Pi BPI-F3 (256-bit VLEN) demonstrating considerable performance gains over upstream Llama.cpp. This work is supported by the RISC-V Software Ecosystem (RISE), with the vectorized kernels being upstreamed to Llama.cpp along with the test infrastructure.
Bio: (Adeel Ahmad). I am a compiler engineer at 10xEngineers, working on enabling the compilation of LLMs and vision models for custom hardware/accelerators using IREE, an MLIR-based AI compiler. I have experience in writing optimized kernels for RISC-V Vector (RVV) and custom hardware, LLVM middle-end and backend development.
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wueHans: A Full-Stack Open-Source RISC-V Gaming Console and SoC Architecture
Non-blind submission #NHUVSR in Europa. On Thusrday 11, at 17h15.
Jonathan Hager, Timo Grundheber, Matthias Jung, and Yannik Stamm.
Abstract: To address the lack of hardware sovereignty in proprietary console ecosystems, this paper presents a fully open-source RISC-V gaming platform utilizing a VexRiscv core and Lattice ECP5 FPGA. We implemented a custom SoC featuring dedicated 2D GPU and APU accelerators, supported by a complete LLVM-based toolchain and a high-level Game Development Framework API. Validation through a 48-hour game jam demonstrated the platform’s utility, achieving a stable 640 × 480 at 60 FPS output and high power efficiency for independent development.
Bio: (Jonathan Hager). Received the Bachelor of Science in Computer Science from the Julius-Maximilians-Universität, Gemany, 2025. Since 2025, he is a research assistant at the Computer Engineering group under Prof. Dr.-Ing. Matthias Jung. Amateur radio operator.
Bio: (Timo Grundheber). Master’s student in Computer Science at the University of Würzburg.
Bio: He received the Diploma and PhD degree in electrical engineering from the Technische Universität Kaiserslautern, Germany, in 2011 and 2017, respectively. From 2011 to 2017 he was a researcher at the Microelectronic Systems Design Research Group of RPTU Kaiserslautern. Since 2017 he is with the Fraunhofer Institute for Experimental Software Engineering in Kaiserslautern as Expert Engineer for virtual hardware engineering. In 2018, he received the EDAA Outstanding Dissertation Award for this work. At Fraunhofer IESE in Kaiserslautern, he has been leading many research and industrial projects in the area of embedded systems since 2017 and has published more than 100 papers in relevant journals and conference proceedings. Since 2023, he is professor at the University of Würzburg. Matthias Jung’s scientific focus is on embedded and autonomous systems, especially with a focus on memory architectures, functional safety, and virtual product development of embedded systems through virtual platforms and simulations.
Bio: (Yannik Stamm). Received the Bachelor of Science in Games Engineering from the Julius-Maximilians-Universität, Gemany, 2025. Since 2025, he is a research assistant at the Computer Engineering group under Prof. Dr.-Ing. Matthias Jung.
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Farewell and closing remarks
Organizers’ annoucement in Europa. On Thusrday 11, at 17h30.
Nick Kossifidis, Teresa Cervero, and Andrea Bartolini.
Abstract: Some highlights about the current event and closing remarks.
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Notes for speakers
Blind and non-blind accepted presentations have been associated with keynotes and invited talks into consistent pleanary sessions, spaning the three days of the core conference.
Preparation before the conference:
- At least one author of the presentation must register for the core conference (Tuesday 9 to Thursday 11).
- There are no templates for slides.
- Upload ASAP an update your PDF abstract on the submission web
site:
- To add the authors’ names if the submission was blind.
- To fix typos, if any, if your submission was non-blind.
- Before Friday May 29th, AOE (Anywhere on
Earth):
- Upload your slides as PDF or PPTX on the submission web site.
- Upload your poster as PDF on the submission web site.
At the conference:
- Get in touch with your session chair during the previous half-day, or early on Tuesday for talks of Tuesday 9 morning.
- Your absract, slide and poster (if any) will be published
online as PDFs on the conference web site:
- The abstract will be published as soon as we get it.
- The poster, if any, slightly before, of at the Summit’s opening.
- The slides will be pushed online after the Summit.
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