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RISC-V in space

Thematic session of the RISC-V Summit Europe 2026 about RISC-V in space
Wednesday 10, 16h30-18h00

About the RISC-V in Space session

This thematic session aims at bringing together member companies, space agencies, and academic partners to discuss the technical strategy and ecosystem requirements for adopting RISC-V as the standard architecture for future space missions. The space sector is the ideal playground for RISC-V, leveraging its modularity to balance critical space-specific requirements (radiation hardening, fault tolerance, minimal power consumption) with the rapid pace of terrestrial innovation.

RISC-V offers a unique opportunity for industry to migrate towards non-proprietary, modern, extensible platform, leveraging ecosystem stability, open standards. By unifying diverse requirements, from simple microcontrollers to high-performance payload processors under a single open ISA, RISC-V enables the space sector to retain the rigor of Old Space while unlocking the low power and cost-effectiveness essential for the next generation.

The RISC-V in Space thematic session, organized by the RISC-V in Space Special Interest Group (SIG) as part of the the RISC-V Summit Europe 2026.

Target audience

The RISC-V in Space thematic session is addressed to the entire space value chain:

  • Space Agencies (ESA, NASA, JAXA, ISRO): to set requirements and certification standards.
  • Satellite OEMs & Primes: to define system-level needs for future platforms.
  • Space Transportation & Launchers: to devise new avionic architectures
  • IP & Silicon Vendors: to implement radiation-hardened cores and SoCs.
  • Software Vendors (RTOS, Hypervisors): to ensure software ecosystem readiness.
  • Research & Academia: to drive innovation in fault-tolerance and novel architectures.

Location and schedule

The thematic session will take place at the Summit’s venue on Wednesday June 10, from 16:30–18:00 CET, with the following program:

  • 16h30-16h45 — Opening & Introduction
    • 16:30-16:35 — Welcome Remarks, Gianluca Furano (ESA)
    • 16:35-16:45 — RISC-V in Space SIG Overview & Objectives, Gianluca Furano (ESA) and Fabrizio Magugliani (E4 Computer Engineering)
  • 16:45-17:30 — Keynote Series The Evolution of RISC-V in Space
    • 16:45-17:00 — The Historical Context & Strategic Fit, Gianluca Furano (ESA)
    • 17:00-17:15 — The Hypercomputing Continuum, Antonio Sciarappa (Leonardo)
    • 17:15-17:30 — Industrial Insights, Ted Speers (Microchip) and Sandi Habin (Frontgrade Gaisler)
  • 17:30-18:00 — Round Table “RISC-V Ready for Space”
    • Gianluca Furano, ESA
    • Sandi Habinc, Frontgrade Gaisler
    • Luca Cassano, Politecnico di Milano
    • Ted Speers, Microchip
    • Representative from NASA (remote)
  • 18:00 — Wrap Up

Registration

As part of the RISC-V Summit Europe 2026, the RISC-V in Space thematic session does not require any extra registration. Simply register for the main event to gain access.

Organizers

The RISC-V in Space thematic session is origanized by: