banner

Side Events: Public Workshops & Consortium Meetings

Friday of the week of the RISC-V Summit Europe is the day for project meetings and workshops.

Friday June 28th will be dedicated to the following RISC-V and open source hardware side events:

Side Event 1: CROSSCON & (Secure) Friends

Room: E101/102, 9:00-18:00

Organized by the HORIZON EU-funded CROSSCON Project, this event - “CROSSCON & (Secure) Friends” - will disseminate advances related to RISC-V with a particular focus on the topic of security among a set of EU-funded projects, i.e., CROSSCON, ORSHIN, REWIRE, SPIRS, SecOpera, and others.

Topics of interest: Topics of interest include but are not limited to:

  • Architecture, applications, and implementation technologies for trusted platforms and trustworthy infrastructures
  • Virtualization support for trusted execution
  • Cross-platform standardization of TEEs and interoperability issues
  • TEE support for hardware accelerators
  • Root of Trust design and implementation
  • Use case studies of trusted execution

For the detailed agenda, please visit the Workshop Website.

Side Event 2: TRISTAN Training on EDA Tooling for RISC-V Solutions

Room: E104, 9:00-11:30

Electronic Design Automation tools play a central role for research and development of Processor Families and Hardware Peripherals. The Chips JU-funded project TRISTAN aims to expand and develop RISC-V architecture in Europe to compete with existing commercial alternatives, and focuses on low and mid-end performance RISC-V processors including hardware peripherals, software development and EDA tooling. TRISTAN will provide this free-access training on EDA tooling for RISC-V solutions and will give a glimpse into the TRISTAN EDA tooling landscape, Virtual Platform Modeling for RISC-V Systems, CVE2 Industrial Verification, and shared experiences on IP Design with open-source and commercial tools.

Agenda

09:00 - 09:15 Welcome and Brief Introduction to the TRISTAN EDA tooling landscape
SPEAKER: Bernhard Fischer (Siemens)
This introduction session will give a brief overview of the EDA tools used in TRISTAN and their alignment to a generalized IC design flow, from architecture exploration to synthesis and layout.

09:15-09:45 Virtual Platform Modeling for RISC-V Systems
SPEAKER: Rocco Jonak (MINRES)
Using virtual prototypes and platforms is becoming more and more common both for large SoCs and embedded systems. This session will briefly outline the elements which MINRES is providing to the RISCV ecosystem in that context, and which improvements are in progress as part of the development within the TRISTAN project.

09:45-10:45 CVE2 Industrial Verification
SPEAKER: Florian ‘Flo’ Wohlrab (OpenHW Group), Davide Schiavone (OpenHW Group), Mario Rodriguez(OpenHW Group)
We will give you an overview how to verify a deeply embedded RISC-V CPU, the CVE2 of OpenHW, with open-source tools and convert it to an industrial usable product within a community driven, TRISTAN sponsored open-source project.

10:45-11:15 Experiences on IP Design with open-source and commercial tools
SPEAKER: Sara Bocchio (STMicroelectronics)
First experiences gained during TRISTAN with Open-Source EDA tools and commercial tools for a design use case will be shared showing advantages and limitations of the approaches taken.

Side Event 3: 1st Open-Source RISC-V Software Workshop

Room: E105, 9:00-17:00

History teaches us that any new hardware without good and widely-used software on top has no future. Countless examples exist even from the biggest manufacturers (e.g. Intel Itanium, IBM Cell, …) without even considering competition (e.g Sun Microsystems’s Ultrasparcs, Digital’s Alphas, HP’s …). Regardless of the nostalgia and to ensure RISC-V is successful beyond small controllers, software and -specially- widely used software suites require the focus now to avoid repeating the errors of the past.

This workshop is born to bring together all the researchers and developers in the open-source software arena to showcase their developments and stablish collaborations. This community can provide efficiently and effectively the necessary software in the different application areas where RISC-V can be deployed.

This workshop focuses on software. From hardware simulators/emulators, through OSes/toolchains, to applications and software stacks. A special focus will be devoted to open-source and collaborative projects.

For a detailed program visit the Workshop Website.

Friday Side Events

Information for Registration and Organization.

Extra registration required

Participation to one or several side events requires registration for Friday 28th, and payment of the associated fees to covers breaks and lunch.

Attendees need to book a full-day pass for Friday at 60 Euro at registration.

Workshop Organization Details

Friday June 28th is open for RISC-V and open source hardware side events, e.g. public workshops or private consortium meetings.

The rooms need to be booked by the projects or workshop organizers at cost (including VAT):

  • Full day: 2000 Euro
  • Morning only: 1200 Euro
  • Afternoon only: 1000 Euro