Tutorials and Technical Workgroup Meetings

The week of the RISC-V Summit starts with one day of tutorials and technical workgroup meetings.

The technical work groups of RISC-V get the opportunity to meet face-to-face at this first day of the summit. Those meetings are only open to members.

Additionally there are tutorials that are open to all.

Monday Program Overview

Tutorials

Information on tutorials.

Tutorial Introduction to RISC-V

Walk-in, No registration for Summit required, Room E 101 /102 from 10am – 12pm

Abstract: “Introduction to RISC-V” is crafted as an introduction to the world of RISC-V architecture. This course delves into the core aspects of RISC-V, focusing on its Instruction Set Architecture (ISA), the benefits of its open standard nature, and its extensibility. ‘Introduction to RISC-V aims to provide participants with an overall understanding of the fundamentals of RISC-V, making it ideal for newcomers and those who wish to gain a richer insight into leveraging this cutting-edge technology. Whether you are new to RISC-V or looking to expand your knowledge, this course will equip you with the knowledge and concepts to navigate and utilize RISC-V effectively. Begin your journey with RISC-V here.

Subjects Include:

• What is RISC-V?
• Why RISC-V?
• Software & RISC-V
• How Europe can Engage in RISC-V
• Getting Involved in RISC-V

Content may change. This session is approximately 2 hours. It is free and no registration for the RISC-V Summit EU is required to attend.

Tutorial on X-Heep SoC

Abstract X-HEEP is a RISC-V open-source platform meticulously crafted at the Embedded System Laboratory (ESL) of EPFL. It stands out for its configurability and extensibility, fostering rapid prototyping of custom IPs, which significantly reduces the entry threshold for developers. A pivotal aspect of X-HEEP is its strategic reuse of successful open-source IPs, primarily from renowned entities such as PULP, OpenHW Group, and OpenTitan. This integration not only bolsters the reliability and efficiency of X-HEEP but also enriches its feature set with validated components widely acknowledged in the industry. Users can seamlessly instantiate custom accelerators, co-processors, peripherals, and memory blocks, leveraging the X-HEEP’s versatile extension interface. We will also highlight X-HEEP’s readiness for FPGA implementation and its first tape-out implementation on TSMC 65nm technology, named HEEPocrates. The roadmap ahead and ongoing collaborations will be discussed, showcasing X-HEEP’s commitment to continuous improvement and innovation. The presentation will also spotlight X-HEEP’s strong focus on education, providing essential tools for students to learn how to design custom IPs, integrate them, and develop embedded software. Attendees will gain insights into the practical applications of X-HEEP, supported by demonstrations and case studies showcasing its versatility and efficiency. By the end of the session, participants will have a comprehensive understanding of how X-HEEP’s open-source approach and extendible architecture can streamline the development of customized hardware solutions, foster innovation, accelerate time-to-market for new products, and enrich educational experiences.

Bios Pasquale Davide Schiavone (Davide) is a PostDoc at the Swiss Federal Institute of Technology Lausanne (EPFL) and Director of Engineering of the OpenHW Group. He obtained the Ph.D. title at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group in 2020 and the BSc. and MSc. from “Politecnico di Torino” in computer engineering in 2013 and 2016, respectively. His main activities are on RISC-V CPU design and low-power energy-efficient computer architectures for smart embedded systems and edge-computing devices. He likes to contribute what he does open-source. Since the Ph.D., he delivers training workshops to companies and universities.

Juan Sapriza is a doctoral candidate at the Embedded Systems Laboratory of EPFL. His research focuses on ultra-low-power embedded hardware and software co-design, particularly involving Coarse-Grained Reconfigurable Architectures (CGRAs) and sparse signal processing. Juan is actively involved in several X-HEEP projects and serves as a maintainer of the software stack for the main repository of X-HEEP.

Tutorial on Implementing support for custom RISC-V extensions in LLVM

Slides

Abstract This tutorial will provide a high level overview of how to implement support for custom RISC-V extensions in LLVM. It will guide you through:

• A very rapid summary of the LLVM compilation flow and the parts relevant to custom instruction set extensions.
• The different levels of compiler support, when they would be appropriate, and the relevant trade-offs.
• Implementation approaches and examples
• Assessing the amount of effort required for different types of extensions
• Testing approaches
• Various other tips and guidance

Bio Alex Bradbury is a compiler engineer at Igalia, working within a growing LLVM sub-team largely focused on RISC-V compiler support. He has been heavily involved in the RISC-V ecosystem since its inception, working across the hardware and software stack having previously co-founded lowRISC CIC. He initiated the upstream RISC-V LLVM backend implementation, authoring the initial patchset, acting as upstream code owner, and collaborating with a growing set of contributors. Alex is also well known within the LLVM community for authoring the LLVM Weekly newsletter for the past 10 years.

Tutorial: RISC-V in Education

This presentation provides an overview of how to get started with RISC-V in education. It covers the benefits of using RISC-V in educational settings, including its open standard nature and extensibility. The session explores various resources and tools available for teaching RISC-V, such as development boards, simulators, and educational materials.

Hackathon

RISC-V International is excited to join with its members Codasip and Renesas to host an in person hackathon at RISC-V Summit Europe!

For details and updates please visit the Hackathon Event website.

Technical Workgroup Meetings

Information on technical workgroup meetings. (RISC-V Members only)

DTPM SIG

Debug, Trace, and Performance Monitoring Special Interest Group (SIG) coordinates and prioritizes debug, trace and performance monitoring activities for RISC-V.

Runtime Integrity SIG & Security HC

Runtime Integrity SIG: Explore and propose security mechanisms related to runtime integrity that may be efficiently implemented at the ISA level, to provide strong security guarantees, and bridge the gap between RISC-V and other architectures.

Security Horizontal Committee:

• Promote RISC-V as an ideal vehicle for the security community
• Liaise with other internal RISC V committees and with external security committees
• Create an information repository on new attack trends, threats and countermeasures
• Identify top 10 open challenges in security for the RISC-V community to address
• Propose security committees (Marketing or Technical) to tackle specific security topics
• Recruit security talent to the RISC-V ecosystem (e.g., into committees)
• Develop consensus around best security practices for IoT devices and embedded systems

More info at https://lists.riscv.org/g/security.

SoftCPU SIG

The RISC-V Soft-CPU SIG provides a forum to advance RISC-V as the preeminent ecosystem for FPGA processor and SoC designs. The SIG will not deliver any specifications or standards. It will develop overall strategy and establish priorities, then create task groups to develop any identified outputs.

Composable Extensions (CX) TG

This new TG will define ISA and non-ISA specifications to facilitate the decentralized, cooperative reuse of the custom instruction and custom CSR space, enabling practical reuse, within a system, of multiple, independently authored composable custom extensions (CXs), CX libraries, and CX unit (CXU) logic modules, while also remaining backwards compatible with legacy custom extensions.

CHERI SIG + TG

The CHERI SIG will work on a strategy for adding a capability based security model (CHERI) to the RISC-V ISA. Enabling a capability-based security model will ensure that RISC-V can provide strong security guarantees as well as mechanisms for compartmentalization that are more scalable than traditional MMU/PMP-based techniques. This SIG will work towards defining a CHERI-enabled instruction set, toolchain requirements, programming model and psABI.

Technical Starters Guide for RISC-V

The objective of this presentation is to help technical contributors who are new to RISC-V learn to navigate the information and resources to enable contributions.

Fast Interrupt Task Group

The aim of the Fast Interrupt Task Group is to:

• Develop a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards
• Provide both hardware specifications and software ABIs/APIs.
• Standardize compiler conventions for annotating interrupt handler functions.

RISC-V Labs

RISC-V Labs brings together member companies from across the ecosystem to give developers the resources they need to build and test their software, from porting of existing projects to development of new components that will power the next wave of computing innovation.

RISC-V Lab Partners provide one or more of the following:

• Continuous Integration (CI) testing of open source software projects
• CI testing resources for use by open source communities to use on their projects
• “Sandbox” instances of RISC-V physical and virtual hardware for open source communities and projects

Scalar Efficiency SIG

This group works to identify opportunities to improve code size and/or performance by defining new instructions that combined the semantics of existing instructions that commonly occur together.

RISC-V Developer Boards Program

The RISC-V Developer Boards program serves to evangelize and promote the RISC-V architecture by partnering with RISC-V hardware vendors to donate hardware to projects to:

• Drive success of RISC-V member products and services, to enable operating system distributions support,
• Grow upstream open-source software community adoption,
• Build educational resources,
• Embrace emerging technologies which use the RISC-V architecture, and
• Foster software ecosystem engagement and good-will.

Participant projects will submit a plan of usage and be required to document their results using the board. In addition, RISC-V vendor members are running their own programs and coordinating with RISC-V International.

HPC SIG

Computer simulation of real-world processes and entities is crucial for scientific discovery and engineering. High Performance Computing (HPC) is the workhorse that not only enables these workloads, but furthermore is also crucial for AI and ML models. The HPC community have recently reached exascale (the ability for a supercomputer to perform a billion billion calculations per second), but as we move further into the exascale era there are other challenges, such as an increased focus on decarbonising our workloads, faced by the HPC community that requires the rethinking of existing approaches.

The RISC-V HPC SIG focusses on bringing RISC-V to HPC, with our belief that the unique flexibility offered by RISC-V will be crucial to the HPC community in meeting the challenges that it faces. In this SIG we are identifying and exploring the high priority areas in the RISC-V ecosystem that must be addressed to drive adoption in HPC, as well as building awareness of RISC-V in HPC and acting as a network for participants working in this area.

Special Interest Group on High-Performance Computing (HPC). More info at https://lists.riscv.org/g/sig-hpc.

Marketing Committee

The Marketing Committee seeks to generate awareness and adoption of the RISC-V open collaboration ecosystem and adoption of RISC-V technologies, be an advocate for the organization, and help build the RISC-V brand. They also provide input into the strategic marketing plan, RISC-V marketing activities, and assistance on the execution of marketing efforts. The RISC-V Marketing Committee should be considered by it’s members as an extension of their own marketing department for RISC-V related products, solutions, tools, etc.

Server Platform TG

The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in a RISC-V server platform.

RISC-V in Space

The first RISC-V in Space Workshop was organized by the European Space Agency (ESA) in December 2022 in the Netherlands, focusing on the use of RISC-V technology in the space domain. ESA has delegated the organization and execution of a second workshop to Frontgrade Gaisler and it will take place on 2-3 April 2025 in Gothenburg, Sweden. This two day event will include a single technical track (baseline) and an exhibition, and is has been fully endorsed by ESA and RISC-V International. As preparation for this second installment of the workshop, the organizers are inviting interested parties to join them in a preparatory meeting to form a technical committee and brainstorm technical topics to be included in the call for paper. You are more than welcome to join the technical committee or to contribute the organization of the event.

Agenda:

• presentation of RISC-V in Space workshop concept
• presentation of the 2022 event and lessons learned
• forming of a technical committee
• forming of technical topics for the call for papers

Hosts: Mr Roland Weigand - European Space Agency; Mr Sandi Habinc - Frongrade Gaisler

Link to past event