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Program

The program will span an entire week around the main conference program.

The main conference program along with the Expo will run from Tuesday to Thursday. Before the program starts, Monday will provide access to tutorials for RISC-V newcomers and technical workgroup meetings for members. Friday will complete the exicting program with side events around research project presentations, workshops and project meetings.

Monday, June 24
09:00-17:00

RISC-V tutorials (beginner and intermediate), RISC-V technical workgroup meetings (members only)

17:00-18:30

RISC-V International Annual General Meeting (members only)

Tuesday, June 25 to Thursday, June 27

Conference plenary program, Keynotes, Panels, Lightning Talks, Expo, Demo Theatre, Social Event

Friday, June 28

Side Events (Workshops and Project Meetings)

Schedule

Tuesday, June 25th
09:00-09:40
Welcome
09:00 - Welcome
09:15 - RISC-V in 2024 - Calista Redmond, RISC-V International
9:40-10:30
Keynotes
09:40 - tba
10:00 - tba
10:15 - tba
10:30-11:30
Break, Booth, Posters
10:30 - Break, Booth, Posters
11:30-12:00
Keynotes
11:30 - RISC-V State of the Union - Krste Asanović, SiFive
12:00-12:15
Talks
12:00 - Optimizing Data Transport Architectures in RISC-V SoCs for AI/ML Applications - Frank Schirrmeister, Arteris
12:15-12:30
Talks
12:15 - Enhancing convolutional neural network computation with integrated matrix extension - Jim Chun-Nan Ke, Andes Tech
12:30-14:00
Lunch, Booth, Posters & Demos
12:30 - Lunch, Booth, Posters & Demos
14:00-14:30
Invited
14:00 - The intelligent wave: How a growth in advanced and accelerated compute will drive adoption of RISC-V - Edward Wilford, Omdia
14:30-15:00
Talks
14:30 - Towards Neuromorphic Acceleration through Register-Streaming Extensions on RISC-V Cores - Simone Manoni, University of Bologna
14:45 - PerfXLM: A LLM Inference Engine on RISC-V CPUs - Chiyo Wang, PerfXLab Technologies
15:00-16:00
Break, Booth, Posters & Demos
15:00 - Break, Booth, Posters & Demos
16:00-16:15
Talk
16:00 - Use of RISC-V to develop multiprocessor host subsystems for accelerated platform with In Memory computing based on NVM memories for AI inference answering functional safety requirements for industrial and automotive applications - Giulio Urlini, STMicroelectronics
16:15-17:00
Lightning Talks
16:15 - Lightning Talks
17:00-17:15
Panel Introduction Keynote
17:00 - RISC-V: Charting the Future of AI/ML with Open Standards and Global Collaboration - Philipp Tomsich
17:15-18:00
Panel
17:15 - Accelerating AI Innovation with RISC-V
18:00 - sponsored by Codasip
Wednesday, June 26th
09:00-10:15
Keynotes
09:00 - RISC-V - Success factors & opportunities for dependable automotive applications - Thomas Böhm, Infineon
09:30-10:15
Keynotes
09:30 - tba
09:45 - tba
10:00 - tba
10:15-10:30
Talk
10:15 - tba
10:30-11:30
Break, Booth, Posters & Demos
10:30 - Break, Booth, Posters & Demos
11:30-11:45
Invited
11:30 - Updates from the RISC-V Software Ecosystem (RISE) Project - Larry Wikelius, RISE
11:45-12:30
Talks
11:45 - Optimizing Software for RISC-V - Nathan Egge, Google
12:00 - GCC 14 RISC-V Vectorization Improvements and Future Work - Robin Dapp, Ventana Micro
12:15 - Towards Automated LLVM Support and Autovectorization for RISC-V ISA Extensions - Philipp van Kempen, Technical University of Munich
12:30-14:00
Lunch, Booth, Posters & Demos
12:30 - Lunch, Booth, Posters & Demos
14:00-14:15
Invited
14:00 - Navigating Tomorrow's Roads: Aligning RISC-V to Automotive Requirements - Alex Kocher, Quintauris
14:15-15:00
Talks
14:15 - Real Time additions to the CVA6 Core - Nicolas Tribie, Bosch FR
14:30 - SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications - Michael P Rogenmoser, ETH Zurich
14:45 - Breaking the RISC-V MCUs ecosystem barriers - Giancarlo Parodi, Renesas Electronics
15:00-16:00
Break, Booth, Posters & Demos
15:00 - Break, Booth, Posters & Demos
16:00-16:45
Talks
16:00 - Bringing Tier-1 support for Rust to 64-bit RISC-V Linux. - Daniel Silverstone, Codethink Ltd
16:15 - tba
16:30 - tba
16:45-17:15
Panel Introduction Keynote
16:45 - tba - Georgi Kuzmanov, Chips JU
17:15-18:00
Panel
17:15 - How can Europe engage more in RISC-V?
20:00 - Social Event @ Tonhalle
Thursday, June 27th
09:00-09:30
Keynote
09:00 - T(h)ales in Open Source Hardware - Bernhard Quendt, Thales
09:30-10:30
Talks
09:30 - We had 64-bit, yes. What about second 64-bit? - Mathieu Bacou, Télécom SudParis
09:45 - Open-Source Development Platform for RISC-V Application-Specific Instruction-Set Processors - Kari Hepola, Tampere University
10:00 - Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis - Simon Rokicki, Irisa
10:15 - Bring your code to RISC-V accelerators with SYCL - Max Brunton, Codeplay
10:30-11:30
Break, Booth, Posters & Hackathon Demos
10:30 - Break, Booth, Posters & Hackathon Demos
11:30-12:30
Talks
11:30 - tba
12:30-14:00
Lunch, Booth, Posters & University Demos
12:30 - Lunch, Booth, Posters & University Demos
14:00-14:15
Invited
14:00 - tba
14:15-15:00
Talks
14:15 - Instrument Control & Data Processing for high-reliable ‘New Space' instruments - Gerard Rauwerda, Technolution
14:30 - Mercek a RISC-V based Multithread - Multicore GPGPU with Texture Unit - Oğuzhan Vatansever, TÜBİTAK
14:45 - Open Virtual Platforms APIs Enable High Quality, Easily Maintained RISC-V Processor Models - Larry Lapides, Synopsys
15:00-16:00
Break, Booth, Posters & University Demos
15:00 - Break, Booth, Posters & University Demos
16:00-16:15
Invited
16:00 - RISC-V and Trusted Electronics: a match made in heaven? - Johanna Baehr, Fraunhofer AISEC
16:15-17:30
Talks
16:15 - Standardizing CHERI for RISC-V - Tariq Kurd, Codasip
16:30 - CHERI RISC-V: A Case Study on the CVA6 - Bruno Sa, University of Minho - Centro ALGORITMI/LASI
16:45 - RISC-V Hypervisor extension formalization in Sail - Lowie Deferme DistriNet, KU Leuven
17:00 - Open-source RISC-V Input/Output Physical Memory Protection (IOPMP) IP - Luis Cunha, University of Minho
17:15 - Unique Program Execution Checking: Formal Security Guarantees for RISC-V Systems - Alex Wezel, RPTU Kaiserslautern-Landau