Conference Program

The main conference program along with the Expo will run from Tuesday to Thursday.

Speakers of Tuesday June 24th

Welcome

Stefan Wallentowitz, Hochschule München

Plenary on Tuesday June 24th at 09:00.

RISC-V in 2024

Calista Redmond, RISC-V International

Plenary on Tuesday June 24th at 09:15.

All-in-One RISC-V AI compute engine

Roger Espasa, Semidynamics Technology Services SL

Plenary on Tuesday June 24th at 09:40.

Abstract

In this talk we will describe Semidynamic’s solution for future-proof AI compute, based on the combination in a single element of Semidynamics RISC-V core, vector and tensor unit. We will cover the new tensor instructions implemented by Semidynamics, how these can be used in AI convolutions and matrix multiplication. We will also cover the need for the vector unit in modern AI models, such as LLMs, to properly run activations.

Biography

Roger Espasa is the CEO and founder of Semidynamics, an IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion(tm) misses, both targeted at HPC and Artificial Intelligence. Prior to the foundation of the company, Roger was Technical Director/Distinguished Engineer at Broadcom leading a team designing a custom ARMv8/v7 processor on 28nm for the set-top box market. Before its experience at Broadcom, from 2002 to 2014, Roger led various x86 projects at Intel as Principal Engineer: SIMD/vector unit and texture sampler on Knights Ferry (45nm), L2 cache, texture sampler on Knights Corner (22nm), the out-of-order core on Knights Landing (14nm) and the Knights Hill core (10nm). From 1999 to 2001 he worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture. Roger got his Phd in Computer Science from Universitat Politècnica de Catalunya in 1997 and has published over 40 peer reviewed papers on Vector Architectures, Graphics/3D Architecture, Binary translation and optimization, Branch Prediction, and Media ISA Extensions. Roger holds 9 patents with 41 international filings.

Take advantage of RISC-V without adding risk to your next generation SoC and system design

Thomas Heurung, Siemens EDA

Plenary on Tuesday June 24th at 10:00.

Abstract

The power and flexibility of RISC-V is having a profound impact on how SoC designers and silicon architects are implementing their current and future designs. This newfound freedom however, opens up challenges in the areas of exploration, verification, validation and deployment of the design, as well as the team expertise needed to deliver a working product on schedule.

In this presentation, we will explore how Siemens, with collaboration with our RISC-V ecosystem partners, and customers, has been able to eliminate these new sources of risk and improve schedule predictability for RISC-V based designs. From the earliest stages of design, through functional validation and production deployment, Siemens’ solutions support RISC-V. Our long history of working with our customers on both standard and custom processor designs and SoCs translates directly to RISC-V work.

Siemens EDA is dedicated to helping companies engineer a smarter future faster with its industry-leading portfolio of EDA software, hardware and services. Technology support specifically targeted to RISC-V includes these Siemens EDA platforms: Veloce, Questa, Catapult, and Tessent.

Biography

Since graduating with a degree in electrical engineering in 1997 from Friedrich-Alexander University in Erlangen, Thomas Heurung has been assisting customers in solving various challenges in industrial applications. His first engagements were with the development of electrical systems for automobiles and airplanes, embedded software for distributed control systems, and eventually moved on to the development of complex electronic systems and components. After transitioning from Synopsys to Mentor Graphics in 2004, which became part of Siemens AG in 2017 and is now known as Siemens Electronic Design Automation, he held various responsibilities such as global business development and establishing and leading technical sales in Europe and India for the Capital and Volcano product lines. Since 2020, he is serving as Technical Director, responsible for the technical sales of semiconductor and electronic systems development tools at Siemens EDA in EMEA.

Solving the RISC-V puzzle - Optimal performance with zero risk

Ron Black, Codasip

Plenary on Tuesday June 24th at 10:15.

Abstract

Customization is the way forward for getting the performance we need in processors. It is evident, and uniquely supported by the flexible and scalable RISC-V ISA. More and more IP vendors realize they need to provide some level of configuration or customization. But there is a big elephant in the room. Is the quality always where it needs to be? We must ensure custom core designs can be exhaustively verified once the desired performance level is reached. By taking our verification efforts to the next level, we empower you to implement custom instructions without risk, reducing the time to market for a verified core.

Biography

Dr. Black, CEO at Codasip, has over 30 years of industry experience. Before joining Codasip, he has been President and CEO at Imagination Technologies and previously CEO at Rambus, MobiWire, UPEK, and Wavecom. He holds a BS and MS in Engineering and a Ph.D. in Materials science from Cornell University. A consistent thread of his career has been processors including PowerPC at IBM, network processors at Freescale, security processors at Rambus, and GPUs at Imagination.

RISC-V State of the Union

Krste Asanović, SiFive

Plenary on Tuesday June 24th at 11:30.

Optimizing Data Transport Architectures in RISC-V SoCs for AI/ML Applications

Ashley Stevens , Arteris

Plenary on Tuesday June 24th at 12:00.

Abstract

This presentation will illustrate the challenges and solutions of data-transport architectures for artificial intelligence/machine learning (AI/ML) in the context of embedded vision architectures and discuss implementation aspects for Networks-on-Chips (NoCs) for RISC-V-based System-on-Chips (SoCs). AI/ML and Embedded Vision architectures present unique challenges in data transport architectures to procure all relevant data from off-chip DRAMs and efficiently store and transport them in caches to allow efficient computing on SoCs and systems of chiplets.

These challenges directly translate into specific requirements for NoC implementation, impacting performance, power consumption, and cost, efficiently addressing the challenges posed by what the industry calls the “memory wall” – the much faster improvement of processor vs. DRAM memory access speed. In addition, for the automotive and industrial application domains, special considerations regarding safety and resilience need to be considered to allow for ISO26262 and related certifications.

Enhancing convolutional neural network computation with integrated matrix extension

Jim Chun-Nan Ke, Andes Tech

Plenary on Tuesday June 24th at 12:15.

Abstract

This proposed architecture introduces a novel matrix extension and customized quantization instructions for Risc-V CPUs, specifically for general convolutional neural network (CNN) applications. This presentation emphasizes the design of the matrix multiplication/accumulation instructions, aiming to achieve scalability/portability across diverse VLEN machines (VLEN agnostic). The key objectives include higher computing capacity, intensified compute intensity and reduced memory access bandwidth requirements. Furthermore, this work proposes an associated 2D-load/store unit (LSU) for matrix tiling enhancements and the Zero-Overhead Boundary handling to streamline user configuration cycles. Additionally, a novel quantization instruction is introduced, contributing to the acceleration of the entire CNN computations. By synergistically integrating these state-of-the-art techniques, the architecture demonstrates significant performance enhancements. Preliminary performance data underscores the benefits and the potential acceleration of General Matrix Multiply (GeMM) and convolutional neural network (CNN) workloads. Notable performance metrics include kernel loop MAC utilization rate surpassing 75% and compute intensity up to 9.6 (VLEN 512), achieved through advanced software unrolling techniques.

Demo Theatre Talk: Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions

Pedro Marcuello, Semidynamics Technology Services SL

Demo Theatre on Tuesday June 24th at 12:40.

Abstract

In this talk, we will present Semidynamics custom tensor instructions and we will show how to use them to accelerate machine learning workloads. Furthermore, we will also show the speedups achieved on real deep learning models when using the new tensor instructions.

Biography

Pedro Marcuello joined Semidynamics in 2018 and currently he is the IP Director of the company. Pedro participated in the architectural design and the RTL development of both Atrevido and Avispado RISC-V family cores, the Vector Unit and the Tensor Unit. Before joining Semidynamics, Pedro worked in Broadcom as IC Design Engineer implementing an ARM v7/v8 multicore for the set-top-box market segment, and previously, Pedro worked at Intel labs for 12 years in multiple research projects. Pedro holds both MSc and PhD in Computer Science from the Universitat Politècnica de Catalunya.

Demo Theatre Talk: Breaking the RISC-V Processor Customization Barrier with Formal Verification

Sven Beyer, Siemens EDA

Demo Theatre on Tuesday June 24th at 12:50.

Abstract

RISC-V is gaining immense traction in the embedded space, with more and more application cores emerging as well. This broad range of available cores – coupled with the ability to include custom extensions – opens unprecedented innovation opportunities in the SoC domain. However, verification of those highly parameterized core instances, including their custom extensions, remains a time-consuming challenge. (Keep in mind that state-of-the-art processor DV was mostly practiced by only a few big players in the market prior to RISC-V!) In this presentation we will show an automated, customer-proven flow from ISA level specifications of custom extensions through their exhaustive formal verification; and demonstrate results on popular open-source cores.

Demo Theatre Talk: Enhancements to SiFive’s Essential product line

Pete Lewin, SiFive

Demo Theatre on Tuesday June 24th at 13:00.

Abstract

Pete Lewin from SiFive will discuss enhancements to its popular Essential product line, bringing new performance and flexibility to embedded applications, automotive and the IoT.

Demo Theatre Talk: Andes High Value RISC-V Processors and Their Application

Frankwell Lin, Andes

Demo Theatre on Tuesday June 24th at 13:10.

Abstract

Andes continues to develop full spectrum RISC-V IP portfolio, ecosystem, and specific domain applications. In this presentation, we will report on the latest out-of-order RISC-V processor, in-order RISC-V processor products, automotive-grade ISO26262 certified new products, as well as middle-end and entry-level new CPU IP. A platform test-chip based on Andes RISC-V multiprocessor AX45MP and RVV vector processor, designed and manufactured in TSMC 7nm process, along with its evaluation board will be demonstrated. Additionally, Andes’ accepted posters and speeches at the 2024 RISC-V Summit Europe will be highlighted.

Biography

Frankwell Lin, Chairman of Andes Technology, started his career being as application engineer in United Microelectronics Corporation (UMC) while UMC was an IDM with its own chip products, he experienced engineering, product planning, sales, and marketing jobs with various product lines in UMC. In 1995, after four years working on CPU chip product line as business director, he was transferred to UMC-Europe branch office to be its GM when UMC reshaped to do wafer foundry service, he lead UMC-Europe to migrate itself from selling IDM products to selling wafer foundry service. In 1998, after 14 years working in UMC, Frankwell switched job to work in Faraday Technology Corporation (Faraday), he lead ASIC business development as starting, then on-and-off leading ASIC implementation, chip backend service, IP business development, industry relationship development (IR), as well as Faraday’s spokesperson, in 2004, he started to lead the CPU project spin off operation of Faraday. Frankwell became co-founder of Andes Technology Corporation in 2005 when it was found up, he formally took position to be Andes’ President since 2006 and got promoted as Chairman and CEO in 2021.

Demo Theatre Talk: Driving SoC Innovation with Synopsys RISC-V Solutions

Rich Collins, Synopsys

Demo Theatre on Tuesday June 24th at 13:30.

Abstract

RISC-V is reshaping the tech industry as more companies choose to leverage the customizability, scalability and flexibility offered by the RISC-V ISA and ecosystem. RISC-V provides opportunities for innovation, giving SoC architects and software developers the ability to define new products and create a high degree of differentiation in their product portfolios. However, successful development of RISC-V based SoCs requires expertise in digital design, verification, and embedded systems, along with proven EDA, verification and software development tools. Learn how Synopsys’ comprehensive, ready-to-use design, verification, and ARC-V™ processor IP solutions enable designers to achieve their IC design goals and accelerate time to market for their RISC-V based SoC.

Biography

Rich Collins is the product management director for the ARC-V™ RISC-V based processor portfolio at Synopsys and has over 30 years of experience in embedded semiconductor R&D, product marketing and business development. Rich holds an MBA from Duke University’s Fuqua School of Business and a BSE in Electrical Engineering from Duke University.

The intelligent wave: How a growth in advanced and accelerated compute will drive adoption of RISC-V

Edward Wilford, Omdia

Plenary on Tuesday June 24th at 14:00.

Abstract

Research firm Omdia’s recent report, RISC-V Processors Market Tracker, examines the projected growth of the ISA in six key verticals; automotive, communications, consumer, enterprise, industrial, and mobile. In each of these, the growth of RISC-V is forecast to be driven by increases in the volume and value of what Omdia terms ‘applied intelligence’, encompassing processors for AI, connectivity, and rich embedded applications. This talk will present Omdia’s findings and forecasts for RISC-V in these markets, as well as the firm’s forecast for processors by application.

Towards Neuromorphic Acceleration through Register-Streaming Extensions on RISC-V Cores

Simone Manoni, University of Bologna

Plenary on Tuesday June 24th at 14:30.

Abstract

Convolutional Spiking Neural Networks (S-CNNs) have emerged as a promising bio-inspired solution to address the need for low- latency, energy-efficient object-detection and image recognition systems. However, S-CNNs pose a challenge to traditional CPUs, GPUs and neural network accelerators due to their inherent sparsity, spike-based communication between neurons and complex activation functions. We explore a novel mapping methodology for S-CNNs on a general-purpose open-source RISC-V core equipped with Indirection Streaming Semantic Registers, a lightweight ISA extension for accelerating sparse-dense linear algebra. Our methodology shows that it is possible to achieve speedups on S-CNNs microkernels up to 10.23× on a dense baseline and up to 7.68× on an optimized dense implementation for high degrees of sparsity of input features.

PerfXLM: A LLM Inference Engine on RISC-V CPUs

Chiyo Wang, PerfXLab Technologies

Plenary on Tuesday June 24th at 14:45.

Abstract

This paper introduces a Large Language Models (LLMs) inference engine on RISC-V CPUs, and describes its design principle, implementation and optimizations methods. We presents the key components of the framework, the hardware support, and the main optimization proposals. Experiment results shows that: we have verified the feasibility and efficiency of our engine on RISC-V CPUs.

Demo Theatre Talk: Introduction of XuanTie RISC-V

James Shi (Qinghao Shi), Alibaba Damo (Hangzhou) Technology Co., Ltd.

Plenary on Tuesday June 24th at 15:10.

Abstract

In this presentation, we will introduce the latest progress in the XuanTie ecosystem, including our IP products, software stack construction, and industry collaborations. We invite you to discuss with us the latest developments in RISC-V.

Biography

I am James Shi. I am currently a principal STE at Alibaba Damo academy, my current main focusing is on kernel & Linux OS testing for Xuantie RISC-V processors. Some of my work is also related wtih validating CPU memory models, system integration testing and performance testing for Xuantie C908 / C920 / C907 With RSIC-V community, I am leading activities for Arch Compatibility Test SIG since 2023 and Certification Steering Committee since 2024, I been dedicated on formalizing the contribution process for ACT tests, and promoting ACT to wider audience.

Demo Theatre Talk: Accelerate RISC-V DSA design with Virtual Board Builder

Hualin Wu, Terapines Technology (Wuhan) Co., Ltd.

Plenary on Tuesday June 24th at 15:20.

Abstract

Designing a Domain Specific Architecture (DSA) is challenge because it requires evaluating the performance of the software before DSA hardware is ready. It also requires repeatedly tuning the micro-architecture and adding custom instructions to meet specific needs. This demo show presents a novel approach to build a virtual RISC-V IP core and SoC with GUI tools, add custom instructions to accelerate AI applications, and profile performance gain with our integrated cycle accurate simulator. The complete workflow can be done in just a few minutes with our sophisticated RISC-V based ESL toolchain.

Biography

Co-Founded Terapines Technology in 2020. Previously worked at Andes Technology, S3 Graphics and Imagination Technologies as a compiler engineer for more than 10 years.

Demo Theatre Talk: AI custom Software/Hardware Interface improving performance 5-10x 

Keith Graham, Codasip

Plenary on Tuesday June 24th at 15:30.

Abstract

The RISC-V open standard enables customized heterogeneous processor solutions targeting performance, area, and energy. In this demo, through Custom Compute, a small core transforms sensor data through DSP operations and detects anomalies through Artificial Intelligence (AI). Without Custom Compute, the system’s energy profile increases and may not complete at the desired frequency, technology node, or time. A new Software / Hardware Interface defined using Codasip Studio with bounded customization increased application performance 5x while vastly limiting the verification effort and risk.

Biography

Over my thirty-eight career, I’ve gone from designing workstations, selling semiconductors, small business owner, senior instructor teaching embedded systems and computer architecture, to leading Codasip’s University Program. The common link between all these jobs is my Electrical Engineering degree.

In the late 1980s, it appeared that every company was developing their own processor architecture, but quickly in the 1990s, the vast different architectures shrank as software binary compatibility became a priority. Over the following years, Dennard Scaling and Moore’s Law broke, resulting in technology evolving from homogeneous to heterogeneous processing where each application is optimized by its specialized processor. With the advent of RISC-V’s Open Standard, a new golden era of processor engineering is upon us to design these specialized solutions.

Demo Theatre Talk: ESWIN EIC7700X/7702X, Pioneer of RISC-V Computing Solution

Bo Wang, Beijing ESWIN Computing Technology Co., Ltd.

Plenary on Tuesday June 24th at 15:40.

Abstract

ESWIN EIC7700X and EIC7702X are excellent SoCs with superior performance. With 64-bit RISC-V high-performance CPU (processors) and self-developed efficient NPU, they support full-stack floating-point computing and comprehensively accelerating generative LLM. The products have rich peripheral expansion interfaces, strong capabilities of audio and video processing, and can be well applied in the field of computer vision (CV) and AI PC.

Biography

Vice Chairman of Beijing ESWIN Computing Technology Co., Ltd., with 30 years’ experiences in the Semiconductor industry, 25 years in Intel, rich experiences in R&D, PM, Marketing & Sales, etc.

Use of RISC-V to develop multiprocessor host subsystems for accelerated platform with In Memory computing based on NVM memories for AI inference answering functional safety requirements for industrial and automotive applications

Carmine Cappetta , STMicroelectronics

Plenary on Tuesday June 24th at 16:00.

Abstract

In a constantly evolving world, where deployment of intelligence at the edge presents many challenges (higher computing capacity and memory, and lower energy consumption), the NeuroSoC project, started in September 2022, has the ambition to develop a Multi-Processor System on Chip prototype able to answer those challenges. It will also cope with mass volume production and low-cost requirements, using a solid, mature, and qualified reliable Phase Change Memory technology. The NeuroSoC prototype will be based on FD-SOI 28nm CMOS technology and will integrate an Analog In Memory Computing Neural Processing Unit, named AIMC IMNPU unit , a local digital processing subsystem, and functional safe multiprocessor host subsystems based on an enhanced version of existing RISC-V microprocessor. Thus, it will enable the support of most of the wide set of edge-AI applications targeting a highly efficient power consumption profile.

2’ Lightning Talk: Synopsys Solutions Drive RISC-V Success

Larry Lapides, Synopsys

Plenary on Tuesday June 24th at .

Abstract

Developing a RISC-V based SoC, both hardware and software, requires a range of expertise and use of best-known methods and technologies. Synopsys provides solutions from the beginning of the project, architecting the SoC, through implementation including RISC-V processor IP and verification of self-built RISC-V processors, through to software development on the SoC.

Biography

Larry is currently Executive Director of Product Management, responsible for the Imperas branded products in Synopsys. He was VP Worldwide Sales & Marketing, and a member of the founding team, for Imperas Software Ltd., up until the 2023 acquisition of Imperas by Synopsys. Prior to Imperas, Larry held VP Sales roles at a couple of EDA startups, and was vice president of worldwide sales during the run-up to Verisity’s IPO (the top performing IPO of 2001 in the U.S.), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire Verification (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Prior to moving into marketing and sales, Larry spent 9 years working on infrared photodiode design and fabrication. Larry has been on the Clark University School of Management (SOM) Advisory Council since 2003, and was an Entrepreneur-in-Residence at Clark during Fall 2006, when he developed and taught the course on Entrepreneurial Communication and Influence. Larry holds a BA in Physics, with General Distinction in Physics, from the University of California Berkeley, a MS in Applied and Engineering Physics from Cornell University and a MBA from Clark University.

2’ Lightning Talk: Andes RISC-V, Everywhere in Our Life!

Vince Wu, Andes Technology

Plenary on Tuesday June 24th at .

Abstract

Discover Andes’ success stories with renowned customers and the latest updates in RISC-V technology.

2’ Lightning Talk: Exploring Accelerator Integration With Core-V eXtention InterFace (CV-X-IF) for Kyber

Alessandra Dolmeta, CEA

Plenary on Tuesday June 24th at .

Extended Abstract Slides

Biography

Alessandra Dolmeta graduated in Electronic Engineering in 2020 and in Microelectronics in 2022, both at the Politecnico di Torino. She is now a PhD student in Electrical, Electronic and Communications Engineering at the Polytechnic University of Turin, in collaboration with Telsy. The main focus of her research activity is the design of hardware architectures for post-quantum cryptography integrated on RISC-V, with the aim of speeding up and optimising PQC algorithms. Currently, she is working as a visiting PhD student at the CEA/Leti laboratory for Security of Hardware Components in Grenoble.

2’ Lightning Talk: ESWIN Computing’s RISC-V Innovation

Bo Wang, Beijing ESWIN Computing Technology Co., Ltd.

Plenary on Tuesday June 24th at .

Abstract

Introduction of ESWIN Computing Company and our RISC-V technologies and innovations. Launch of RISC-V Computing Solution - EIC7700X/7702X.

Biography

Vice Chairman of Beijing ESWIN Computing Technology Co., Ltd., with 30 years’ experiences in the Semiconductor industry, 25 years in Intel, rich experiences in R&D, PM, Marketing & Sales, etc.

2’ Lightning Talk: A Space-Grade Fault-Tolerant Radiation-Hardened MPSoC

Jan Andersson Nerén, Frontgrade Gaisler

Plenary on Tuesday June 24th at .

Abstract

The GR765 is the fifth-generation European space-grade microprocessor in development by Frontgrade Gaisler. It is a RISC-V based multi-processor system-on-chip with NOEL-V RV64 RISC-V processor cores. It supports DDR2/3/4 SDRAM and NAND Flash memory with advanced error detection and correction capabilities. The communication interfaces include a SpaceWire router, SpaceFibre, Ethernet, MIL-STD-1553, and CAN-FD interfaces.

Biography

Mr Jan Andersson Nerén. M.Sc in Computer Engineering focused on digital design and embedded systems. Director of Engineering at Frontgrade Gaisler, where he oversees hardware and software development efforts and leads implementation of the system-on-chip architecture roadmap. Jan’s accomplishments include development and verification of the GR740 quad-core LEON4FT, UT700 LEON3FT, and GR712RC dual-core LEON3FT space-grade microprocessors and maintenance of the open-source hardware GRLIB IP Library that includes the NOEL-V RISC-V processor model.

2’ Lightning Talk: Enabling Innovation with RISC-V – The Perspective of the Leading Debug Tool Supplier

Markus Herdin, Lauterbach GmbH

Plenary on Tuesday June 24th at .

Abstract

Markus Herdin will talk about Lauterbach’s commitment to enabling innovation in embedded systems by providing debugging tools the industry needs, for the entire silicon lifecycle. With RISC-V on the rise, Lauterbach is here to enable innovation with RISC-V.

Biography

Markus Herdin, Head of Marketing at Lauterbach GmbH, is a seasoned market and business development professional with a background in the test and measurement and wireless industries. His experience includes market and business development, product management, product development, corporate strategy and research. He also serves as an advisor to start-up companies. Markus holds a Ph.D. in Electrical Engineering and an MBA from the University of Chicago Booth.

2’ Lightning Talk: Exciting possibilities with the SiFive HIFive Premier P550 development board

Dany Nativel, SiFive

Plenary on Tuesday June 24th at .

Abstract

Dany Nativel from SiFive will discuss the exciting possibilities with the SiFive HIFive Premier P550 development board that will be widely available shortly after the show, The new board is the most powerful RISC-V development board yet, enable development on a wide range of projects and designs.

2’ Lightning Talk: Using SmartWave for RISC-V based device emulation

Klaus Strohmayer (semify GmbH), Tristan

Plenary on Tuesday June 24th at .

Abstract

An Efficient Way of Developing and Testing Embedded Systems

Biography

Klaus Strohmayer is a seasoned semiconductor professional with over 20 years of experience in digital design and verification. As the founder of semify, he has established a company that provides comprehensive digital design and verification services, including the latest microcontroller architectures like RISC-V. Klaus has a proven track record of successfully bringing ideas to life, having previously worked for renowned semiconductor companies such as Infineon, Dialog Semiconductor, and NXP, where he played an instrumental role in developing working ASICs. He has recently spearheaded the development of USound’s first ASIC from FPGA-based prototyping to tapeout, meeting demanding timelines, tight area, and power consumption constraints. Klaus remains actively involved in digital design and verification projects and is also a lecturer at University of applied science Joanneum in Graz.

2’ Lightning Talk: One Platform for RISC-V Software and Hardware Optimizations

Ze Fan, TeraPines

Plenary on Tuesday June 24th at .

Abstract

Open source toolchain currently plays an important role in RISC-V software infrastructure. However, in areas where RISC-V could bring the most difference, which is DSA, open source tools like gcc and llvm often fall short. We present a one-stop solution for both general-purpose and domain-specific language compiler optimization, debugging and performance evaluation. This helps our customers achieve superior performance, faster custom ISA extension iterations and architecture evaluation.

Biography

Joined Terapines Technology as CEO in 2023. Previously worked as ASIC engineer at HiSilicon and NVIDIA, followed by portfolio manager and executive director in private equities in the semiconductor industry.

RISC-V: Charting the Future of AI/ML with Open Standards and Global Collaboration

Philipp Tomsich, VRULL

Plenary on Tuesday June 24th at 17:00.

Accelerating AI Innovation with RISC-V

Gianna Paulin, Axelera AI, Xie Tao, Peking University, Roger Espasa, Semidynamics,
Iakovos Stamoulis, Think Silicon S.A.

Plenary on Tuesday June 24th at 17:15.

Abstract

AI is a fast evolving space, and realising its huge potential requires levels of compute innovation only possible with RISC-V. This session brings prominent members of the RISC-V AI ecosystem together to explore how the RISC-V ISA will form the common language for AI innovation, how it can deliver the performance and efficiency necessary across applications from the edge to the cloud, and the potential of software and hardware codesign. The RISC-V ecosystem is already delivering the technologies that will underpin the future of AI, come to this session to find out more!

Speakers of Wednesday June 25th

Harnessing the Power of Collaboration Across Continents and Markets: A Panel Discussion (Room E119)

Yuning Liang, CEO, Deep Computing, Makeljana Shkurti, Growth Strategy & Ecosystem Relations at VRULL GmbH, Florian Wohlrab, CEO Open HW Group

Plenary on Wednesday June 25th at 08:00.

Abstract

Room: E119 (first floor above expo)

For any community, collaboration is a key success factor. When contributors with diverse skills, perspectives and backgrounds come together, it should lead to a meaningful exchange of unique perspectives and ideas, which in turn drives and accelerates innovation and creativity. Yet optimizing a diversity of perspectives is not a given. The RISC-V community benefits from the contributions of more than 4,300 members around the world. Capitalizing on and optimizing the strengths and contributions of these members takes an ability to reach across continents and leverage the perspectives of members working across different industries/markets, from AI to automotive to HPC, mobile and space. In this special event, industry leaders share their experiences working across continents and industries to drive impactful solutions making a meaningful difference for the RISC-V community.

RISC-V - Success factors & opportunities for dependable automotive applications

Thomas Böhm, Infineon

Plenary on Wednesday June 25th at 09:00.

RISC-V Adoption: Powered by AI

Balaji Baktha, Ventana Micro Systems

Plenary on Wednesday June 25th at 09:30.

Abstract

This talk explores the potential of RISC-V for high-performance AI applications. Balaji will discuss Ventana’s approach to building scalable AI solutions, including: High-Performance Cores: Leveraging server-grade RISC-V cores for demanding AI workloads., Integration of Right-Sized Acceleration: Integration of vector/tensor units for AI tasks., Streamlined Software Stack: Exploring how the open-source RISC-V ecosystem can facilitate efficient development. Future-Proof Design: Examining the advantages of RISC-V and chiplets for building scalable and adaptable AI solutions.

Open-Source at BOSC: Achievements and Challenges

Bao Yungang, Beijing Institute of Open Source Chip

Plenary on Wednesday June 25th at 09:45.

Abstract

The Beijing institute of Open-Source Chip (BOSC), founded in 2021, develops strong ties with academia and industry. In addition to the successful development of industry’s open source and high-performance RISC-V CPU core XiangShan, a core mission of BOSC is to promote and contribute to the open-source chip ecosystem, covering not only design tools (such as agile development tools and open-source EDA tools), but also verification methodologies (such as open-source verification) and education (such as the One Student One Chip (OSOC) Initiative). This presentation will introduce 3-5 key contributions that BOSC has made or plans to make to the open-source chip ecosystem in terms of exploration, achievements and lessons learned.

Biography

Yungang Bao is a professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the deputy director of ICT, CAS. Prof. Bao founded China RSIC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture and computer systems. He is leading the XiangShan project (https://github.com/OpenXiangShan/XiangShan ), which aims to build an open-source high performance RISC-V core. He launched the One Student One Chip (OSOC) Initiative in 2019. His work was published on top conferences and journals such as ASPLOS, Communication of the ACM, HPCA, ISCA, MICRO etc. and was selected to IEEE Micro Top Picks. He was the winner of CCF-Intel Young Faculty Award of the year for 2013 and the winner of CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.

The Silicon Commons — Build Together, Build Well and Build Securely

Gavin Ferris, lowRISC

Plenary on Wednesday June 25th at 10:00.

Abstract

Throughout industry, there is a noticeable increase in the adoption of open source designs — including RISC-V cores such as IbexⓇ — in commercial SoCs. Companies of all sizes are finding that they can innovate more quickly by leveraging, and contributing to, this vibrant ecosystem. In this presentation we’ll describe the benefits collaboration can bring to the security of all devices — from the simplest microcontrollers through to complex multi-chiplet architectures. In particular we’ll explain how lowRISC’s Silicon CommonsⓇ approach has enabled OpenTitanⓇ, developed by a consortium of industry leaders and academics, to reach commercial availability and is now enabling the Sunburst project to drive security by design through adoption of RISC-V with CHERI extensions.

The First Study of the Impact of Codee on SiFive’s LLVM RISC-V Development Ecosystem

Manuel Arenaz, Codee

Plenary on Wednesday June 25th at 10:15.

Abstract

The widespread industry adoption of the open RISC-V instruction set architecture requires a robust, mature RISC-V software development ecosystem. The upstream LLVM developer tools for RISC-V are evolving rapidly, but still need further improvements to compete with the well-established ARM and x86 architectures. Codee is a new automatic code inspection tool to help developers optimize C/C++/Fortran codes. This is the first work evaluating the impact of Codee on the LLVM RISC-V ecosystem. The results show up to 7.5x performance boost of well-known open-source codes targeting SiFive’s P470 processor using single-core optimizations for vectorization and memory efficiency. The authors are not aware of a similar approach in LLVM and RISC-V and believe Codee is a new and revolutionizing solution that makes the ecosystem even better.

Demo Theatre Talk: Exploring RISC-V architectures with VPSim, a virtual prototyping environment with the best trade-off between simulation speed & accuracy

Lilia Zaourar, CEA

Plenary on Wednesday June 25th at 10:40.

Abstract

With the increase of complexity of computing systems, virtual prototyping is widely adopted as an efficient and cost-effective solution for early hardware/software co-design and co-validation. VPSim, a virtual prototyping environment developed by CEA List, is designed to meet industrial needs: VPSim provides the best possible trade-off between accuracy and performance (simulation speed) enabling early design space exploration of complex systems, electronics boards, and integrated circuits. With a strategy of open source the tool, we will introduce its key features and development roadmap to allow full system simulation with different IPs, including Arm, RISC V, a NoC and several memories for different HPC and embedded needs, to assess performances and enable exploration.

Biography

Dr. Lilia Zaourar is a CEA expert in co-design techniques for Computing Architectures at CEA LIST. She received an MS and PhD in Operational Research and Computer Science from the University Joseph Fourier, Grenoble, in 2007 and 2010, respectively. She developed various optimization algorithms for the design and test of integrated circuits. Then, she was a temporary teaching and research assistant at the SoC department in Computer Science PARIS 6 Laboratory, Sorbonne University, from 2010 to 2012. She was involved in developing optimization strategies for the resource-sharing problem to test embedded memories. She joined the CEA LIST in 2012 and has participated in various national, European, and industrial research projects on real-time mixed-criticality systems, optimization strategies of runtime software for heterogeneous HPC and microservers, and FPGA emulation. She led Modelling and Simulation activities within the first phase of the European Processor Initiative (EPI) project. She is currently involved in the second phase of EPI on co-design and exploration. Her research interests cover combinatorial optimization and operational research techniques with a special focus on optimization problems for electronic design automation and high-performance embedded systems, as well as testing and security. She is the project leader of the working group “integrated system optimization” funded by the French institution CNRS. She has been a SAMOS, SC, PMBS, and CoDit technical programs member. She has served as General Chair for Hipeac/Rapido 2023, 2024, and General Chair of the 50th Euromicro DSD/SEAA 2024 conference.

Demo Theatre Talk: Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips

Markus Goehrle & Michael Schleinkofer, Lauterbach GmbH

Plenary on Wednesday June 25th at 10:50.

Abstract

RISC-V cores can be found in more and more chips - as the main CPU(s) or as a companion core together with other CPU architectures. Each chip and core supplier can decide individually which functions its RISC-V core(s) support and how they are integrated into the overall system. While the complexity of SoCs grows with the number of cores and the number of different core architectures, the challenges for embedded developers grow even more with operating systems, hypervisors, and other software running on multiple cores. In this presentation experts of Lauterbach, market leader for development tools and strategic member of the RISC-V foundation, show how developers can overcome these challenges with the right tools and debug strategies. They explain how to debug cores from RISC-V and other architectures simultaneously via one debug interface and one debug probe to gain insight into the entire embedded system. The presentation covers real-time on- and off-chip tracing for all major RISC-V trace systems as well as the utilization of standardized RISC-V debug and trace interfaces. All in all, the attendee learns that multicore debugging with RISC-V cores is not rocket science and that there are efficient methods to master even complex chips with complex software configurations.

Biography

M.Sc. Markus Goehrle studied Electrical Engineering and Information Technology at the Technical University of Munich and graduated with an M.Sc. degree. Since 2015 he has been working at Lauterbach as a System Engineer and since 2017 in the RISC-V Debug and Trace team. As a member of the RISC-V Debug/N-Trace workgroups, he contributed significantly to the RISC-V Debug Standard as well as the RISC-V N-Trace Specification. He is also a member of the RISC-V Debug, Trace, and Performance Monitoring Special Interest Group.

M.Sc. Michael Schleinkofer studied Computer Science at the OTH Regensburg and graduated with an M.Sc. degree. Since 2019 he has been working at Lauterbach as a System Engineer in the RISC-V Debug and Trace team. As a member of the RISC-V E-Trace workgroup, he contributed significantly to the RISC-V E-Trace Encapsulation Specification, and he is also a member of the RISC-V Debug, Trace and Performance Monitoring Special Interest Group.

Demo Theatre Talk: UnityChip Verification: Open-Source RISC-V Verification at BOSC

Shan Liu, Beijing Institute of Open Source Chip

Plenary on Wednesday June 25th at 11:00.

Abstract

As chip designs become increasingly complex, the cost of verification rises, presenting significant challenges for verification. In response to this trend, UnityChip verification has emerged as an innovative solution aimed at lowering verification barriers, improve verification productivity, and reducing engineering costs. This presentation provides an overview of the development, implementation methodology and current status of UnityChip verification at BOSC. It takes Xiangshan RISC-V CPU as a case study to showcase the feasibility and accomplishments of UnityChip verification, highlighting its potential impact on future RISC-V chip verification practices.

Biography

Shan Liu is a skilled IP developer with six years of experience in the semiconductor industry. Formerly a technical leader at Intel, she now leads the Memory Subsystem team at BOSC. Shan specializes in external memory, Network-on-Chip, CPU emulation, FPGA verification, and FPGA acceleration.

Demo Theatre Talk: KVM device assignment for virtual machines using the RISC-V IOMMU

Andrew Jones, Ventana Micro Systems

Plenary on Wednesday June 25th at 11:10.

Abstract

The RISC-V IOMMU provides capabilities supporting device assignment, which is the provision of host devices to virtual machines where they appear to the guest operating systems as though they have been physically attached. Beyond the restriction of device DMAs to guest memory, the RISC-V IOMMU, in conjunction with the RISC-V AIA, additionally supports directing interrupts to guest VCPUs, which is a feature also referred to as irqbypass. We demonstrate device assignment with the RISC-V IOMMU including its irqbypass support on a Linux/KVM host running on a QEMU machine model.

Biography

Andrew Jones is a Principal Software Engineer at Ventana Micro Systems Inc. Andrew has nearly 20 years of software engineering experience with the majority being in the enterprise virtualization domain building standards-based software stacks and test frameworks. At Ventana, Andrew currently contributes to the SBI and FFH specifications, to the KVM, Linux, OpenSBI, and QEMU software components, and to the KVM and Linux selftests and kvm-unit-tests test frameworks.

Updates from the RISC-V Software Ecosystem (RISE) Project

Larry Wikelius, RISE

Plenary on Wednesday June 25th at 11:30.

Abstract

RISE (RISC-V Software Ecosystem) launched on May 31 last year with 13 initial members. Since this launch RISE has had tremendous growth in membership as well as in impact to the overall RISC-v Software Ecosystem. This keynote presentation will provide an update on RISE, highlight key contributions to RISC-V open-source communities, address additional impact areas RISE is investing in and discuss future plans.

Biography

I represent Qualcomm as a Governing Board member of RISE and serve as Treasurer. I am a Senior Director in the Qualcomm Standards and Industry Organization (QSIO) and currently lead Qualcomm’s engagements related to RISC-V software. Over my career I have been active in many industry organizations spanning both Arm and RISC-V and have lead software engineering teams at a range of server and silicon companies. I have a B.S. in Computer Science from the University of Minnesota and an MBA from Northeastern University in Boston.

Optimizing Software for RISC-V

Nathan Egge, Google

Plenary on Wednesday June 25th at 11:45.

Abstract

The RISC-V ISA contains several extensions that provide efficient instructions for domain specific optimization, including the V (vector), Zb{a,b,c,s} (bit manipulation) and Zvk (vector crypto) ratified extensions. This talk will look at best practices for writing optimized software for RISC-V including CPU feature detection, techniques for vector length specific (VLS) and agnostic (VLA) algorithms, QEMU as a verification tool, and a methodology (with open source tooling) for performance and correctness testing of RISC-V specialized routines. Where possible, concrete examples will be provided along with resources that can be applied to any open source project.

GCC 14 RISC-V Vectorization Improvements and Future Work

Robin Dapp, Ventana Micro

Plenary on Wednesday June 25th at 12:00.

Abstract

GCC has made good progress in supporting all major RISC-V features during the last two years. This talk details the support of the RISC-V Vector Extension and highlights changes since GCC 13. It focuses on the current status in GCC 14, design decisions and performance as well as ongoing and planned optimization work for GCC 15.

Towards Automated LLVM Support and Autovectorization for RISC-V ISA Extensions

Philipp van Kempen, Technical University of Munich

Plenary on Wednesday June 25th at 12:15.

Abstract

The RISC-V instruction set architecture (ISA) is popular for its extensibility. However, a quick exploration of instruction candidates fails due to the lack of tools to auto-generate embedded software toolchain support. This work establishes a semi-automated flow to generate LLVM compiler support for custom instructions based on a C-style ISA description language. The implemented Seal5 tool is capable of generating support for functionalities ranging from baseline assembler-level support, over builtin functions to compiler code generation patterns for scalar as well as vector instructions. The approach is demonstrated using the Core-V instruction set extensions and custom SHA-256 operations. The autogenerated LLVM toolchain reduces development times drastically while performing similarly or better compared to the existing, manually implemented Core-V reference LLVM toolchain on a wide variety of benchmarks.

Navigating Tomorrow’s Roads: Aligning RISC-V to Automotive Requirements

Alex Kocher, Quintauris

Plenary on Wednesday June 25th at 14:00.

Real Time additions to the CVA6 Core

Nicolas Tribie, Bosch FR

Plenary on Wednesday June 25th at 14:15.

Abstract

The CVA6 is an Open Source RISC-V core, primarily intended for general purpose applications, such as Linux support. We added some features to its internal architecture to make it more suitable for real-time workloads: new scratchpad memories, new peripheral bus, and PMP / MMU split. This submission presents the architectural choices we made, along with the achieved performance in automotive applications.

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications

Michael P Rogenmoser, ETH Zurich

Plenary on Wednesday June 25th at 14:30.

Abstract

In the last decade, we have witnessed exponential growth in the complexity of control systems for safety-critical applications (automotive, robots, industrial automation) and their transition to heterogeneous mixed-criticality systems (MCSs). The growth of the RISC-V ecosystem is creating a major opportunity to develop open-source, vendor-neutral reference platforms for safety-critical computing. We present SentryCore, a reliable, real-time, self-contained, open-source mega-IP for advanced control functions that can be seamlessly integrated into Systems-on-Chip, e.g., for automotive applications, through industry-standard Advanced eXtensible Interface 4 (AXI4). SentryCore features three embedded RISC-V processor cores in lockstep with error-correcting code (ECC) protected data memory for reliable execution of any safety-critical application. Context switching is accelerated to under 110 clock cycles via a RISC-V core-local interrupt controller (CLIC) and dedicated hardware extensions, while a timer-based direct memory access (DMA) engine streamlines sensor data readout during periodic control loops. SentryCore was implemented in Intel’s 16nm process node and tested with FreeRTOS, ThreadX, and RTIC software support.

Breaking the RISC-V MCUs ecosystem barriers

Giancarlo Parodi, Renesas Electronics

Plenary on Wednesday June 25th at 14:45.

Abstract

The significant re-work to port an application software, the lack of viable key items like low-cost hardware platforms for validation and test, hardware abstraction layer stacks, availability of integrated free-of-charge IDEs with integrated toolchains, reliable and committed debug support: all these pose a threat and create adoption barriers for a broader adoption of RISC-V in the microcontroller space.

This can hinder engineers from getting hands-on experience with the RISC-V platform, slow down the expansion of RISC-V within the microcontroller broad market, and further delay its momentum.

During this presentation, attendees will learn how Renesas contributes to the expansion of the RISC-V ecosystem for MCUs by deploying high quality devices and tools including a fully supported and free of charge IDE with compiler toolchain, low-cost prototyping hardware, and enabling support on commercial environments behind the proof-of-concept phase.

Demo Theatre Talk: Introducing Sonata — the new open source platform for CHERIoT development

Greg Chadwick, lowRISC

Plenary on Wednesday June 25th at 15:10.

Abstract

Sonata is a development system designed to enable the evaluation of CHERIoT, a RISC-V extension (including a reference core and RTOS) developed by Microsoft which eliminates most common memory safety issues. In this presentation we will demonstrate Sonata’s features including the CHERIoT IbexⓇ core and a variety of peripherals (I2C, SPI, GPIO, PWM, UART, and DMA). Sonata has been designed by lowRISC, as part of the Sunburst Project, and is fully open source (available on GitHub under an Apache 2.0 license). It is designed for use on Artix-7 FPGAs and specifically targets the Sonata board designed by NewAE which we’ll be using for this demonstration. This work is funded by and done in collaboration with DSbD (Digital Security by Design) / UKRI.

Demo Theatre Talk: The NOEL Processor Line

Jan Andersson Nerén, Frontgrade Gaisler

Plenary on Wednesday June 25th at 15:20.

Abstract

The NOEL-V processor is a European processor model that has been a available for a number of years, providing support for an extensive set of RISC-V extensions and a super scalar in-order microarchitecture. The NOEL-V processor is now being complemented by the NOEL3 processor model from Frontgrade Gaisler. The NOEL3 provides an alternative to address resource constrained, and many-core, applications. The talk presentation will highlight the features and differences between the two processor products.

Biography

Mr Jan Andersson Nerén. M.Sc in Computer Engineering focused on digital design and embedded systems. Director of Engineering at Frontgrade Gaisler, where he oversees hardware and software development efforts and leads implementation of the system-on-chip architecture roadmap. Jan’s accomplishments include development and verification of the GR740 quad-core LEON4FT, UT700 LEON3FT, and GR712RC dual-core LEON3FT space-grade microprocessors and maintenance of the open-source hardware GRLIB IP Library that includes the NOEL-V RISC-V processor model.

Bringing Tier-1 support for Rust to 64-bit RISC-V Linux.

Joshua Zivkovic, Codethink and Lukas Wirth, Ferrous Systems

Plenary on Wednesday June 25th at 16:00.

Abstract

The Rust Project supports a large number of targets for the Rust compiler and tooling. This support is separated into levels called “tiers”. Tier-1 is the top tier with the greatest amount of commitment from the project. In order for platforms to qualify for tier-1 status there is a significant set of conditions which must be met. Our project, in conjunction with RISE, is to bridge the gap between tiers one and two, to elevate the status of 64-bit RISC-V Linux support to tier-1.

This talk will serve as a small introduction of the Rust quality assurance methods. It will also cover the RISC-V specific work that has been done to date, the current status of the platform support, and what work remains to be done to complete tier-1 support. We will cover any platform-specific bug fixes and development work done to enable support, and we will outline ways in which the RISC-V community could engage with the Rust ecosystem to continue to ensure continued support once tier-1 status is achieved.

We will also discuss the involvement of RISE in the RISC-V and Rust communities, along with our impression of how the Rust programming language could play a significant role in the advancement of RISC-V uptake.

RISC-V@BSC: Fostering RISC-V strategy in the EU through Research, Innovation & Education

Teresa Cervero, BSC

Plenary on Wednesday June 25th at 16:15.

Abstract

The openness of RISC-V ISA is an enabler for moving research and business further than before. That is the main reason why RISC-V plays a central role on the European’s technology strategy targeting sustainability, autonomy, competitiveness, and sovereignty. Aligned with this strategy, and being one of the actors in pushing this, Barcelona Supercomputing Center has been actively promoting RISC-V adoption in Europe with a strong focus on research, innovation, and education. In addition to its contributions as partner in relevant EU HPC projects, BSC is designing and developing its own RISC-V catalog of technologies. Without forgetting the VPU, as BSC RISC-V flagship, this talk highlights its integration with the evolution of the Lagarto core family as a pathway towards the next generation of high-performance accelerators (moving from a single core to a multi-core platform, plus the different optimizations applied for being compliant with the demands of the HPC-wise domains).

Biography

Teresa Cervero got her PhD in Telecommunication Engineer by the Univ. of Las Palmas de Gran Canaria (Spain) in 2013 with a thesis focused on dynamic reconfiguration based on FPGAs for video and hyperspectral image processing. She joined Barcelona Supercomputing Center (BSC-CNS) in 2020 as hardware coordinator of the MareNostrum Experimental Exascale Platform (www.meep-project.eu) project, funded by EuroHPC JU. Currently she is responsible for the LOCA initiatives (Laboratory for Open Computer Architecture) with the aim of fostering inter-departmental and international collaboration at BSC, as part of the Severo Ochoa Programme. In addition to that, she is member of the Red-RISCV network (http://www.red-riscv.org/) and the Steering Committee of the RISC-V Summit Europe (https://riscv-europe.org/). She also contributes to HPC open hardware ecosystem as vice-chair of the RISC-V SIG-HPC and by organizing events that put together professionals interested in the field to present new ideas, novelties on different layers of the stack, and products. These events also facilitate sharing knowledge, experience, and networking among the participants.

Vitamin-V: Expanding Open-Source RISC-V Cloud Environments

Ramon Canal, Universitat Politècnica de Catalunya

Plenary on Wednesday June 25th at 16:30.

Abstract

Among the key contributions of Vitamin-V (2023-2025 Horizon Europe project), we develop a complete RISC-V open-source software stack for cloud services with comparable performance to the cloud-dominant x86 counterpart. In this paper, we detail the software suites and applications ported plus the three cloud setups under evaluation.

Biography

Ramon Canal is a full professor and the director of the Chips Professorship at UPC. He previously worked at Sun Microsystems in 2000, he was a Fulbright visiting scholar at Harvard University and a visiting professor at the University of Cyprus in 2019/2020. His research focuses on reliability and security. He has been program committee member in several editions of HPCA, ISCA, MICRO, DATE, HiPC, IPDPS, ICCD, ICPADS, CF. He has been co-general chair of HPCA 2016 and IOLTS 2012. He has been track co-chair for DATE 2019 and 2020. He has been financial co-chair of ETS 2022. He is currently an associate editor of the ACM Transactions on Architecture and Code Optimization, the IEEE Transactions on Computers and the Journal of Parallel and Distributed Computing.

Chips JU and RISC V - vision, actions, challenges

Georgi Kuzmanov, Chips JU

Plenary on Wednesday June 25th at 16:45.

How can Europe engage more in RISC-V?

Alexandra Kourfali, EuroHPC Joint Undertaking, Christian Reitberger, Matterwave Ventures, Peter Gielda, Antmicro Teresa Cervero, Barcelona Supercomputing Center

Plenary on Wednesday June 25th at 17:15.

Abstract

RISC-V holds significance for Europe due to its potential to foster innovation, enhance technological sovereignty, and stimulate economic growth within the region. By embracing RISC-V, European countries can reduce their dependency on foreign technologies and proprietary architectures, thereby enhancing their autonomy in critical sectors such as telecommunications, cybersecurity, and data processing. However, to fully realize the benefits of RISC-V, Europe must engage more actively in the development and deployment of RISC-V technologies. This panel will explore the opportunities and challenges that Europe faces in adopting RISC-V, and discuss strategies to promote the widespread adoption of RISC-V within the region.

Social Event @ TonHalle München

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Plenary on Wednesday June 25th at 19:30.

Abstract

Join this event and enjoy a networking evening in a relaxed atmosphere to meet like-minded people while enjoying free food from a food truck and (two) free drinks. TonHalle München is located in the Werksviertel-Mitte, where Pfanni dumplings used to be produced and has become a party spot. The old factory buildings were not demolished, but completely renovated by artists and creatives. Today, the former industrial buildings house affordable studios and workshops. Used as a warehouse for millions of potatoes in Pfanni’s day, the TonHalle now exudes a unique spirit for every event.

Location: TonHalle München, Atelierstraße 24, 81671 Munich

Getting there : 20 min. by taxi or 40 min. by public transport from the conference venue MOC.

PLEASE BRING YOUR TICKET TO GET DRINK VOUCHERS AND WEAR YOUR NAME BADGE TO GET FOOD DURING THE EVENING.

Speakers of Thursday June 26th

How to leverage Open Source in Industry

Jean-Roch Coulon, Thales

Plenary on Thursday June 26th at 09:00.

Abstract

Open Source HW enables a community of diverse partners (research / university, industry) to elaborate a processor together, fostering innovation and resulting in a faster and more efficient development. How to prevent the processor from buggy or rogue commits resulting in out of control repository threatening its industrial usage (delay, cost, …). How to support industrial Intellectual Property in Open Source product? This conference will present a solution.

Biography

Jean Roch Coulon is RISC-V Architect at Thales group in France, he designed processors to add security in ARM, SPARC, proprietary and now RISC-V implementations. Expert in processor, toolchain, security, cryptography or code size density. His main contributions in RISC-V are the 32bits version of CVA6 (CV32A6), CV-X-IF and verification. He is an OpenHW group committer; developing, reviewing and merging CVA6 and CORE-V-VERIF pull requests.

Industry Academia Collaborations on Open Source Hardware Explained

Frank K. Gurkaynak, ETHZ

Plenary on Thursday June 26th at 09:15.

Abstract

Open source hardware has gained a lot of momentum, and based on my experience as part of the PULP team at ETH Zürich, I will explain aspects of openness at architecture, design tools, and manufacturing for IC design and how these support our collaborations with industry and other partners.

Biography

Frank has obtained his B.Sc. and M.Sc. degree from Istanbul Technical University and his Ph.D. from ETH Zürich. He currently is a senior scientist working on computer architectures in the group of Luca Benini and director of the Microelectronics Design Center at ETH Zürich. He has been involved in the Parallel Ultra Low Power (PULP) platform project since its start in 2013 and has been a vocal advocate for open source activities.

We had 64-bit, yes. What about second 64-bit?

Mathieu Bacou, Télécom SudParis

Plenary on Thursday June 26th at 09:30.

Abstract

High-performance architectures are increasingly heterogeneous and incorporate often specialized hardware. We have first seen the generalization of GPUs in the most powerful machines, followed by FPGAs, and now by many other accelerators such as Tensor Processor Units (TPUs) for Deep Neural Networks, or variable precision FPUs. Recent hardware manufacturing trends make it very likely that specialization will not only persist, but increase. Manually managing this heterogeneity is complex and not maintainable. We therefore propose to revisit how we design both hardware and OS in order to better hide the heterogeneity. To ensure long term viability of our proposal, we propose to entertain the use of 128-bit addressing

Open-Source Development Platform for RISC-V Application-Specific Instruction-Set Processors

Kari Hepola, Tampere University

Plenary on Thursday June 26th at 09:45.

Abstract

Application-specific instruction-set processors (ASIPs) can significantly improve performance and energy-efficiency for a predefined set of priority applications, while also offering high flexibility via compiler-supported programmability. Designing and programming these type of customized processors often relies on hardware-software co-design toolsets that are able to adapt to a high-level processor description, and therefore, offer a robust way of efficiently implementing tailored processors. We present an open-source hardware-software co-design toolset for programming and designing RISC-V based ASIPs. We demonstrate the toolset by designing a custom instruction set extension for three cryptographic algorithms, which results in a 44\% reduction in run time with negligible overheads in clock frequency and area utilization of the synthesized processor implementation.

Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis

Simon Rokicki, Irisa

Plenary on Thursday June 26th at 10:00.

Abstract

The RISC-V ecosystem is quickly growing and has gained a lot of traction in the FPGA community, as it permits free customization of both ISA and micro-architectural features. However, the design of the corresponding micro-architecture is costly and error-prone. We address this issue by providing a flow capable of automatically synthesizing pipelined micro-architectures directly from an Instruction Set Simulator in C/C++. Our flow is based on HLS technology and bridges part of the gap between Instruction Set Processor design flows and High-Level Synthesis tools by taking advantage of speculative loop pipelining. Our results show that our flow is general enough to support a variety of ISA and micro-architectural extensions, and is capable of producing circuits that are competitive with manually designed cores.

Bring your code to RISC-V accelerators with SYCL

Charles Macfarlane, Codeplay

Plenary on Thursday June 26th at 10:15.

Abstract

This talk will show attendees how to overcome proprietary code with RISC-V and SYCL. They will learn how they can achieve code portability and adopt RISC-V hardware without losing their existing work, for greater productivity.

The talk will also highlight the ongoing research into pioneering applications for RISC-V, funded by the EU Horizon programme. AERO and SYCLOPS are two such projects. AERO seeks to enable the future heterogeneous EU cloud infrastructure, while SYCLOPS will bring together the RISC-V and SYCL standards together into a single software stack for the first time.

Demo Theatre: Hackathon Results Demonstration

Megan Lehn - RISC-V International Community Director

Plenary on Thursday June 26th at 10:30.

INNOVATION FORUM

Gianna Paulin, Axelera.ai, Yuning Liang, DeepComputing, Bilal Zafar - 10xEngineers

Plenary on Thursday June 26th at 11:30.

Abstract

The freedom of design enabled by RISC-V is setting off a wave of innovation worldwide, with organizations around the globe developing new solutions and services targeting a range of markets and users from developers to consumers. In this session, we will hear from innovators from different continents who will discuss the innovation behind their solutions and how RISC-V enables them to differentiate in new ways, creating and capturing opportunity.

Board of Directors Technical Leadership, Technical Contributor & Software Awards

Lu Dai, Chair of the Board of Directors, RISC-V International

Plenary on Thursday June 26th at 12:15.

University Demo Theatre: The European Accelerator (EPAC) demonstrator with 3 RISC-V based accelerators

Filippo Mantovanni, BSC

Plenary on Thursday June 26th at 13:00.

University Demo Theatre: RISC-V Instruction Set Explorer (RISE)

Lennart M. Reimann, RWTH Aachen

Plenary on Thursday June 26th at 13:10.

University Demo Theatre: Scale4Edge RISC-V Ecosystem

Paul Palomero Bernardo, EKUT

Plenary on Thursday June 26th at 13:20.

University Demo Theatre: End-to-end flow to automatically generate and integrate RISC-V instruction set extensions (ISAXes)

Tammo Mürmann, TU Darmstadt

Plenary on Thursday June 26th at 13:30.

University Demo Theatre: TETRISC SoC, an fault-tolerant and adaptive quad-core system

Junchao Chen, IHP Microelectronics

Plenary on Thursday June 26th at 13:40.

Ensuring Datapath Integrity and Adherence with Formal Security Verification in RISC-V Implementation

Keerthikumara Devarajegowda, Siemens

Plenary on Thursday June 26th at 14:00.

Abstract

The cornerstone of all security applications is hardware, underscoring the importance of meticulously verifying its security features. As the adoption of RISC-V grows, there is an increasing emphasis on enhancing security features in ASIC and FPGA designs. The protection of sensitive data, including encryption keys, passwords, and biometric information, is paramount, as these are prime targets for security breaches that can lead to costly, damaging, and embarrassing consequences. Challenges in security verification that must be addressed include ensuring data confidentiality, integrity, and inversion, as well as mitigating the exploitation of sneak paths, addressing inefficient verification flows, and managing the added complexity. In this context, formal technology stands out as the sole method that guarantees the security requirements of datapaths are fulfilled. Our methodology introduces a high degree automation to expedite the security verification process, showcasing its applicability and debugging prowess in a RISC-V implementation, specifically with OpenTitan. The paper will present our findings, providing detailed explanations and runtime information, highlighting our approach’s effectiveness in enhancing security verification.

Instrument Control & Data Processing for high-reliable ‘New Space’ instruments

Gerard Rauwerda, Technolution

Plenary on Thursday June 26th at 14:15.

Abstract

We have started the development of a new payload Control & Data Processing Unit (CDPU), an Instrument Control Unit (ICU) with additional data processing capabilities targeted towards ‘New Space’ SmallSats instruments. We defined a modular architecture to allow flexibility in interfaces and functions, with advanced and reliable in-orbit FPGA reprogrammability. The FPGA firmware includes a RISC-V softcore and optional accelerators, allowing for edge processing. This opens the door for payload control, encryption and data processing in space, leveraging the RISC-V ecosystem. The CDPU will act as a hub for (optical) instruments that forms a logical bridge between the instruments and the SmallSat platform. It will offer standardized hardware interfaces for integrated optical instruments, as well as sophisticated facilities for processing the science data before it is sent down to earth. The CDPU also reduces time-to-orbit by removing the need to design an instrument for a specific platform.

VRP: a Variable Precision Accelerator for Scientific Computing Applications

Andrea Bocco, Univ. Grenoble Alpes, CEA

Plenary on Thursday June 26th at 14:30.

Abstract

We develop a RISC-V based accelerator called VRP (VaRiable precision Processor). It efficienctly computes extended precision arithmetic operations, up to 512 bits. This improves convergence issues encountered using linear algebra solvers for scientific applications. This work details the VRP hardware architecture which is used as an accelerator for faster time to solution, with demonstrated reduction of solver execution time by up to 5x.

Open Virtual Platforms APIs Enable High Quality, Easily Maintained RISC-V Processor Models

Larry Lapides, Synopsys

Plenary on Thursday June 26th at 14:45.

Abstract

Functional models of RISC-V processors are critical to the success of RISC-V projects, whether users are developing the processors themselves or licensing the processor IP. These models enable architectural exploration at the beginning of the project, including the addition and optimization of custom instructions, provide a reference model for design verification of the processor, and provide a high performance, instruction accurate model for virtual prototypes for software development. Key requirements for these models are ease of use, flexible configuration, including adding custom instructions, CSRs, etc., and high performance of the models. This paper discusses the use of the open standard Open Virtual Platforms (OVP) APIs used in C/C++ for building high performance processor models.

In this paper model architecture will be discussed, and an overview of the OVP APIs presented. Details of APIs to support specific features will be presented, using the OpenHW Group CVW “Wally” processor being developed by Harvey Mudd College and Oklahoma State University. Examples of adding custom instructions to a RISC-V processor will be presented, including both the technical details and the resource requirements, to demonstrate the ease of use of model development via the OVP APIs. Benchmark simulation results, both for bare metal and OS applications, will be shown for both single processor and multiple processor/hart platforms, to show the linear scalability of performance.

University Demo Theatre: FPGA with a RISC-V processor and a specialized co-processor for CNN computation

Sergio Castillo Mohedano, Lund University

Plenary on Thursday June 26th at 15:10.

University Demo Theatre: Simulate, trace, and evaluate a RISC-V system leveraging very long vectors of 16 thousand bits

Pablo Vizcaino, BSC

Plenary on Thursday June 26th at 15:20.

Demo Theatre Talk: The role of an Open Computing Architecture in EU Digital sovereignty

Luis C. Busquets Pérez, Programme Officer, DG CONNECT, European Commission

Plenary on Thursday June 26th at 15:30.

Abstract

EU Digital autonomy implies the capacity of Europe to act on its own following its values and principles. The complexity of IT layers has ever increased since the outcoming of the first computer but no matter how, any software layer requires an underlying computer to run. The presentation will build on the Open Computing Architecture and how this Architecture will contribute to foster innovation and economic growth in the EU.

Biography

Programme Officer, DG CONNECT, European Commission: Luis C. Busquets Pérez holds a degree in telecommunications engineering (UPC, Barcelona) and a Master in Business Administration (ESADE, Barcelona). For more than 20 years, his professional career has been developed in the ICT sector covering all OSI layers (from fibre optics and semiconductors to IT applications). Previous to his career in the European institutions, he held several positions in marketing and sales for ICT Fortune 500 companies. In 2006, he joined the European Commission services and is currently Programme Officer in DG CONNECT E2, which is the Cloud and Software unit.

University Demo Theatre: CHERI in out-of-order microarchitectures

Franz Fuchs, University of Cambridge

Plenary on Thursday June 26th at 15:45.

RISC-V and Trusted Electronics: a match made in heaven?

Johanna Baehr, Fraunhofer AISEC

Plenary on Thursday June 26th at 16:00.

Abstract

The quest for technological sovereignty underscores the critical need for trusted electronic components within the electronics ecosystem. This talk will discuss the properties required for trusted electronics and explores how the RISC-V architecture aligns with these requirements. The discussion will also cover the current challenges and open problems that need to be addressed to advance this field. Ultimately, the presentation underscores that while hardware security solutions for RISC-V mark a significant step towards achieving trusted electronics, continued innovation and research, which are fostered by the open RISC-V ecosystem, are crucial for developing sustainable and robust security solutions.

Biography

Johanna Baehr is a research associate and project manager at the Fraunhofer AISEC. She is currently working on her doctoral thesis at the Technical University of Munich, dedicating herself to the topic of trusted electronics and IC-Trust, specifically researching hardware reverse engineering and analysis. She strongly supports open-source hardware and is committed to strengthening the position of Germany and the EU in the field of chip manufacturing, chip design and chip security.

Standardizing CHERI for RISC-V

Tariq Kurd, Codasip

Plenary on Thursday June 26th at 16:15.

Abstract

The CHERI Task Group was recently formed within RISC-V International to propose extensions supporting CHERI in the RISC-V ISA. The motivation of these extensions is to enhance RISC-V with features to address memory safety issues which account for over 70% of software vulnerabilities according to Microsoft’s Security Response Center (MSRC). In this presentation, we will provide an overview of the CHERI TG’s present and future work as well as the status of the specifications of the CHERI extensions.

CHERI RISC-V: A Case Study on the CVA6

Bruno Sa, University of Minho - Centro ALGORITMI/LASI

Plenary on Thursday June 26th at 16:30.

Abstract

We report our work on extending the open-source RISC-V CVA6 with CHERI support. Our implementation complies with version 9 of the CHERI RISC-V specification. Currently, we are evaluating and validating our design in an experimental single-core system-on-chip (SoC) in a simulation and FPGA emulation environment. To our knowledge, this will be the first public RISC-V CPU with hardware virtualization and CHERI support. We plan to release our CVA6H-CHERI core as an open-source artifact to the RISC-V and CHERI community.

RISC-V Hypervisor extension formalization in Sail

Lowie Deferme DistriNet, KU Leuven

Plenary on Thursday June 26th at 16:45.

Abstract

RISC-V semantics are specified in prose and in a formal model using a language called Sail. The latter does not yet implement all ratified standard extensions. This work presents an implementation of the missing hypervisor extension into the official Sail model. Necessary modifications and additions to the model are checked for regressions using bundled tests. They are verified using a testsuite that is developed together with the model and with two third-party testsuites. Furthermore, the extracted emulator is able to boot Linux on top of a type 1 hypervisor. Both the formal model implementation and our testsuite may prove to be useful for the development and verification of future systems that implement the H-extension. Finally, the formal model enables future work to create rigorous proofs about hypervisor extension features and the software that relies on them.

Open-source RISC-V Input/Output Physical Memory Protection (IOPMP) IP

Luis Cunha, University of Minho

Plenary on Thursday June 26th at 17:00.

Abstract

This work describes the design and implementation of an open-source I/O Physical Memory Protection (IOPMP) IP compliant with the RISC-V IOPMP Architecture Specification (version 1.0.0-draft5). So far, we have designed and implemented an IP with the mandatory features supporting the Full model. We functionally validated and evaluated this IP within a CVA6-based SoC. Future plans include updating the IP to comply with the ratified specification and expanding its capabilities, such as incorporating additional operation models (e.g., Dynamic-K) and optional features (e.g., MDLCK). Finally, we intend to open-source the IP for the RISC-V community.

Unique Program Execution Checking: Formal Security Guarantees for RISC-V Systems

Alex Wezel, RPTU Kaiserslautern-Landau

Plenary on Thursday June 26th at 17:15.

Abstract

The seemingly endless stream of previously unknown microarchitectural attacks and security flaws in hardware systems is driving the need for more efficient and comprehensive verification techniques. Unique Program Execution Checking (UPEC) is a formal verification methodology that can be used to verify a wide variety of security requirements for hardware at the Register Transfer Level (RTL). With its white-box nature and reusable verification IP, UPEC complements the open-source ecosystem provided by RISC-V. We demonstrate the efficacy of UPEC through a set of selected case studies, covering different threat models and ranging from small RISC-V processors to entire Systems-on-Chips (SoCs).