Program

The program will span an entire week around the main conference program.

The main conference program along with the Expo will run from Tuesday to Thursday. Before the program starts, Monday will provide access to tutorials for RISC-V newcomers and technical workgroup meetings for members. Friday will complete the exicting program with side events around research project presentations, workshops and project meetings.

A preliminary version of the program will be published on May 1st.

Monday, June 24

09:00-17:00

RISC-V tutorials (beginner and intermediate), RISC-V technical workgroup meetings (members only)

17:00-18:30

RISC-V International Annual General Meeting (members only)

Tuesday, June 25 to Thursday, June 27

Conference plenary program, Keynotes, Panels, Lightning Talks, Expo, Demo Theatre, Social Event

Friday, June 28

Side Events (Workshops and Project Meetings)

Confirmed Presentations

The following presentations are confirmed for RISC-V Summit Europe. The schedule will follow soon.

Keynotes

RISC-V State of the Union

Krste Asanović; SiFive

RISC-V - Success factors & opportunities for dependable automotive applications

Thomas Böhm; Infineon

T(h)ales in Open Source Hardware

Bernhard Quendt; Thales

Invited Talks

Navigating Tomorrow's Roads: Aligning RISC-V to Automotive Requirements

Alex Kocher, Quintauris

The intelligent wave: How a growth in advanced and accelerated compute will drive adoption of RISC-V

Edward Wilford, Omdia

RISC-V and Trusted Electronics: a match made in heaven?

Johanna Baehr, Fraunhofer AISEC

Updates from the RISC-V Software Ecosystem (RISE) Project

Larry Wikelius, RISE

Panels

Accelerating AI Innovation with RISC-V

How can Europe engage in RISC-V?

Technical and Industry Presentations

Real Time additions to the CVA6 Core

Nicolas Tribie, Bosch FR

Enhancing convolutional neural network computation with integrated matrix extension

Jim Chun-Nan Ke, Andes Tech

Bringing Tier-1 support for Rust to 64-bit RISC-V Linux.

Daniel Silverstone, Codethink Ltd

Open Virtual Platforms APIs Enable High Quality, Easily Maintained RISC-V Processor Models

Larry Lapides, Synopsys

Breaking the RISC-V MCUs ecosystem barriers

Giancarlo Parodi, Renesas Electronics

Bring your code to RISC-V accelerators with SYCL

Max Brunton, Codeplay

Use of RISC-V to develop multiprocessor host subsystems for accelerated platform with In Memory computing based on NVM memories for AI inference answering functional safety requirements for industrial and automotive applications

Giulio Urlini, STMicroelectronics

Optimizing Data Transport Architectures in RISC-V SoCs for AI/ML Applications

Frank Schirrmeister, Arteris

Instrument Control & Data Processing for high-reliable ‘New Space' instruments

Gerard Rauwerda, Technolution

Open-source RISC-V Input/Output Physical Memory Protection (IOPMP) IP

Luis Cunha, University of Minho

GCC 14 RISC-V Vectorization Improvements and Future Work

Robin Dapp, Ventana Micro

RISC-V Hypervisor extension formalization in Sail

Lowie Deferme DistriNet, KU Leuven

PerfXLM: A LLM Inference Engine on RISC-V CPUs

Chiyo Wang, PerfXLab Technologies

Standardizing CHERI for RISC-V

Tariq Kurd, Codasip

CHERI RISC-V: A Case Study on the CVA6

Bruno Sa, University of Minho - Centro ALGORITMI/LASI

Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis

Simon Rokicki, Irisa

Unique Program Execution Checking: Formal Security Guarantees for RISC-V Systems

Alex Wezel, RPTU Kaiserslautern-Landau

Towards Automated LLVM Support and Autovectorization for RISC-V ISA Extensions

Philipp van Kempen, Technical University of Munich

Open-Source Development Platform for RISC-V Application-Specific Instruction-Set Processors

Kari Hepola, Tampere University

We had 64-bit, yes. What about second 64-bit?

Mathieu Bacou, Télécom SudParis

Mercek a RISC-V based Multithread - Multicore GPGPU with Texture Unit

Oğuzhan Vatansever, TÜBİTAK

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications

Michael P Rogenmoser, ETH Zurich

Towards Neuromorphic Acceleration through Register-Streaming Extensions on RISC-V Cores

Simone Manoni, University of Bologna

Optimizing Software for RISC-V

Nathan Egge, Google