Posters

The list of accepted posters.

Notes for poster presenters

Preparation before the conference:

• Posters shall be printed in A0 format in portrait mode.
• Each presenter shall bring their own poster on site.
• There is no template for posters.
• Make sure that the poster is easy to read from distance and attracts people, use QR codes to link to more content.
• At least one author of the poster must register for the core conference (Tuesday 13 to Thursday 15).

At the conference:

• You will mount your own poster, no own tape allowed, you will get some.
• Each poster will be displayed for a full day.
• Presenters are expected to stand next to their posters during breaks and lunches.
• The exhibition and poster area will be open only during breaks and lunches.

Posters

Sorted by last name of main contact.

CIAMH : Confidentiality, Integrity and Authentication across the Memory Hierarchy
KARIM AIT LAHSSAINE (CEA-LETI)

Towards a Base-Station-on-Chip for 6G Networks: RISC-V Hardware Acceleration of the LOW PHY wireless communication kernels
Javier Acevedo (TU Dresden)

Embedded FPGA-Shell: Emulating RISC-V Architectures at FPGA
Sajjad Ahmed (Barcelona Supercomputing Center)

Enhancing EDA Physical Synthesis Workflows with najaeda for the RISC-V Ecosystem
Christophe Alexandre (keplertech.io)

Implementation of Branch Treatment Strategies in the Ripes RISC-V Simulator
Francisco Alfaro-Cortés (Universidad de Castilla-La Mancha)

Exploring Selective Speculation through Speculation barriers
Herinomena Andrianatrehina (Inria Rennes)

Reliable Hardware Trojan Formal Verification
Christian Appold (DENSO AUTOMOTIVE Deutschland GmbH)

An Efficient Approach for End-to-End Formal Verification of RISC-V CPUs
Laurent Arditi (Codasip)

On Benefits of Modeling the HPDcache in LNT
Zachary Assoumani (INRIA)

ACE: Atomic Cryptography Extension for RISC-V
Roberto Avanzi (Qualcomm, and University of Haifa)

SoC Studio: A User-Centric Framework for Custom System-on-Chip Design, Emulation, and AI Integration
Shayan Baig (Usman Institute of Technology)

Programming and Modeling RISC-V on RISC-V architecture with ChatGPT assistance
Przemyslaw Bakowski (Nantes University)

Reliability in High-Performance Computing: Insights from a RISC-V Vector Processor
Marcello Barbirotta (Sapienza University of Rome)

Verification of CoreSwap: Replacing ARM Cortex-A5 with RISC-V CVA6 in ARM SoC Environment
Muhammad Hammad Bashir (Department of Electrical Engineering, U.E.T Lahore)

How well does RISC-V Perform? Recent comparison data against other architectures
Jeremy Bennett (Embecosm)

SCAR: Selective Cache Address Remapping for Mitigating Cache Side-Channel Attacks
Pavitra Bhade (Indian Institute of Technology)

Call Rewinding Towards RISC-V Specification
Téo Biton (Thales cortAIx Labs)

Comparing Voltage and Clock Glitch Attacks on a RISC-V implementation on FPGA
Roua Boulifa (TIMA)

A Hardware-Based Cache Side Channel Attack Detection Mechanism for RISC-V Processors
Andreas Brokalakis (Technical University of Crete)

RISC-V for HPC: An update of where we are and main action points
Nick Brown (EPCC at the University of Edinburgh)

Programming RISC-V accelerators via Fortran
Nick Brown (EPCC at the University of Edinburgh)

Enabling High Performance RISC-V Software for AI in the Real World
Max Brunton (Codeplay)

V-Seek: Accelerating LLM Reasoning on Open-hardware Server-class RISC-V Platforms
Alessio Burrello (Politecnico di Torino and Università di Bologna)

LLMPoint: A Fast Sampling and Performance Analysis Framework for LLM Inference on RISC-V
Luoshan Cai (Beijing Institute of Open Source Chip)

RuyiSDK - A Integrated and Customizable Toolkit for RISC-V Software Development
Weilin Cai (PLCT)

Evaluation of Optimized PQC Standards ML-KEM and ML-DSA on Sargantana RV64GBV core
Xavier Carril Gil (Barcelona Supercomputing Center)

Status of Fedora’s RISC-V Porting Efforts
Kashyap Chamarthy (Red Hat)

Secure Domain-Specific Debugging on an MCU
Alvin Chang (Andes Technology)

Low Cost and High Efficiency AI Application Based on RISC-V Computing Power and DeepSeek
David Chen (Stream Computing)

HW-extended Containers on FPGA-based RISC-V SoC.
George Christou (Technical University of Crete)

Enterprise Linux Enablement On RISC-V
Isaac Chute (RISC-V International)

On-Device Federated Continual Learning on RISC-V-based Ultra-Low-Power SoC for Intelligent Nano-Drone Swarms
Cristian Cioflan (ETH Zurich)

Pre-silicon Security Analysis of\ RISC-V Processors to Fault Injection Attacks
Damien Couroussé (Univ. Grenoble Alpes, CEA, LIST)

An Open-Source Trusted Execution Environment for Resource-Constrained RISC-V MCUs
Luis Cunha (University of Minho)

Technical presentations for new applications
Shailesh Deshpande (Chiplogictech)

RISC-V-based Acceleration Strategies for Post-Quantum Cryptography
Stefano Di Matteo (CEA-Leti)

TYRCA: A RISC-V Tightly-coupled accelerator for Code-based Cryptography
Stefano Di Matteo (CEA-Leti)

Exploring the Security of an Accelerator integrated with Core-V eXtention InterFace (CV-X-IF)
Alessandra Dolmeta (Politecnico di Torino)

Automating RISC-V Custom Instruction Integration leveraging High-Level Synthesis
Florian Egert (Siemens AG Austria)

A Flexible and Portable Performance Evaluation Framework for Instruction Set Simulations
Conrad Foik (Technische Universität München)

Utilising RISC-V to reduce data centre CPU energy consumption by up to 80% by delivering five fold application performance in general purpose compute.
Andy Frame (VyperCore)

Safe Speculation for CHERI
Franz Fuchs (University of Cambridge)

Leveraging RISC-V Vectorization: Accelerating Java Programs with TornadoVM and OCK
Juan Fumero (The University of Manchester)

RISC-V Cloud Computing Open Experimental Platform
Yue GAO (China Telecom Corporation Limited Research Institute)

Evaluating SYCL Support on RISC-V Multicore Architectures: A First Approach
Carlos Garcia (Complutense University of Madrid)

Microarchitectural signals analysis platform for the implementation of Hardware Security Counters
Lucas Georget (EDF R&D / LAAS-CNRS)

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
Roberto Giorgi (University of Siena)

CVA6 Design Space Exploration on Agilex 7 FPGA
Angela Gonzalez (PlanV)

Integration of a CGRA Accelerator with a CVA6 RISC-V Core for the Cloud-edge
Juan Granja (Universidad Politécnica de Madrid)

Enabling Front-End SoC Integration Automation Flows for Large RISC-V Designs
Bastien Gratreaux (Defacto Technologies)

Using trace based performance models to accelerate customer evaluations
SAMUEL Grove (MIPS Tech LLC)

A Fine-Grained Dynamic Partitioning Against Cache-Based Timing Attacks via Cache Locking
Jeremy Guillaume (UBS)

Implementing out-of-order issue in CVA6 for efficient support of long variable latency instructions
Eric Guthmuller (Univ. Grenoble Alpes, CEA, List)

RISC-V based GPGPU on FPGA: A Competitive Approach for Scientific Computing ?
Eric Guthmuller (Univ. Grenoble Alpes, CEA, List)

RISC-V Architectural Functional Verification
David Harris (Harvey Mudd College)

High Performance RISC-V Processor for Application in Harsh Environments
Malte Hawich (Leibniz Universitaet Hannover, Institute of Microelectronic Systems)

From RustVMM to Kata-Containers: Securing Container Workloads with H-ext Based Virtualization Software
Ruoqing He (ISCAS)

Efficient system-level support for CHERI Capabilities
Mark Hill (Codasip)

Instruction Fusion Limit Study for RISC-V
Elizabeth Ho (University of Cambridge)

FPHUB-RISCV: HUB Floating-Point Unit in RISC-V Platform – Format definition
Javier Hormigo (Universidad de Malaga)

RISC-V Unified Database
Derek Hower (Qualcomm)

Comprehensive Verification of the RISC-V Memory Management Unit: Challenges and Solutions
Yazan Hussnain (10xEngineers)

Comprehensive Lockstep Verification for NaxRiscv SoC integrating RISCV DV, RVLS, and Questa/UVM
Billal IGHILAHRIZ (CEA-LETI)

Towards Efficient Modeling and Validation of Scalable Chiplet-based Platforms
Fatma Jebali (CEA LIST)

Toward industrial grade CHERI enhanced cores
Alexandre Joannou (University of Cambridge)

Vicuna 2.0 : A Configurable RISC-V Embedded Vector Hardware Platform
Jefferson Jones (Vienna University of Technology)

Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches
Victor Jung (ETH Zurich)

Energy & Latency Efficient Dual-Mode AI Accelerator - AGNI Neural Inference Engine
Naman Kalra (IIT Tirupati)

Supporting Sparse Inference in XNNPACK with RISC-V Vector Extension
Alan Kao (Andes Technology)

RISC-V MPU - Address Space Isolation for Latency Critical and/or Resource Constrained Systems
Alexey Khomich (Synopsys Inc)

Vyond: Flexible and Rapid WorldGuard-Based Security Prototyping using Chipyard
Sungkeun Kim (Samsung Research)

How Much Score Could a CoreScore Score if a CoreScore Could Scores?
Olof Kindgren (Qamcom)

Enabling Reconfigurable High-Throughput RISC-V Systems through Barrel-Processing
Dirk Koch (Heidelberg University)

Work-In-Progress: Accelerating Numpy With OpenBLAS For Open-Source RISC-V Chips
Cyril Koenig (ETH Zurich)

RISC-V Solutions for Post Quantum Computing for Machine Readable Travel Documents
Leonidas Kosmidis (Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC))

A Safe and Secure Platform for Autonomous Driving
Leonidas Kosmidis (Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC))

Modular SAIL: dream or reality?
Peter Kourzanov (IMEC)

Commercial Poster: Codasip’s X730 core, the word’s first commercially available CHERI-RISC-V Application Core
Tariq Kurd (Codasip)

Standardizing CHERI-RISC-V, CHERI TG specification and status update
Tariq Kurd (Codasip)

Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6
Umberto Laghi (University of Bologna)

FGMT-RiscV: A fine grained multi threading processor for FPGA systems
Bernhard Lang (Hochschule Osnabrück, University of Applied Sciences)

RISC-V Certification Program Status
Larry Lapides (Synopsys)

Vaquita: A Portable Four Stage Pipeline RISC-V Vector Co Processor
Muhammad Latif (Usman Institute of Technology)

From Research Idea to Tapeout: Challenges of your first real Chip
Yannick Lavan (TU Darmstadt)

Accelerating Quanized LLM Inference for Embedded RISC-V CPUs with Vector Extension (RVV)
Yueh-Feng Lee (Andes Technology)

Improving RISC-V TLB Shootdown Performance
Guy Lemieux (The University of British Columbia)

Agile Formal Verification with Symbolic Quick Error Detection by Semantically Equivalent Program Execution
Yufeng Li (Institute of Computing Technology, Chinese Academy of Sciences)

Toffee: an Efficient and Flexible Python Testing Framework for Chip Verification
Jincheng Liu (Institute of Computing Technology, Chinese Academy of Sciences)

Building the RISC-V Education Ecosystem: A Systematic Educational Contents Design, Remote Laboratories, and Community-Driven Learning
Yunxiang Luo (The Institute of Software, Chinese Academy of Sciences (ISCAS))

Poster: RISC-V system prototyping in the RISER project
Manolis Marazakis (FORTH)

Designing a RISC-V Platform for the HIGHER project based on current and upcoming extensions
Manolis Marazakis (FORTH)

Security assessment methodology for RISC-V cores
Macarena Martinez-Rodriguez (Instituto de Microelectronica de Sevilla (IMSE-CNM), CSIC, US)

Auto-re-vectorization into RISCV Vector Code, from Vector/SIMD Intrinsics Code Written for Other Architectures like x86 AVX or ARM Vector/Neon, Using LLVM Infrastructure
Nisanth Mathilakath Padinharepatt (MIPS)

The REBECCA Hardware/Software Edge AI platform
Iakovos Mavroidis (Technical University of Crete)

Advancing Confidential Computing on RISC-V with the Memory Protection Table
Stefano Mercogliano (University of Naples Federico II)

Optimizing TLS Cryptographic Operations on RISC-V SoC with OpenTitan RoT
Alberto Musa (University of Bologna)

Enabling Syscall Interception on RISC-V.
Ramon Nou Castell (Barcelona Supercomputing Center)

REPTILES: Repeated Tiles of Sargantana, a RISC-V multicore based on OpenPiton
Noelia Oliete-Escuín (BSC)

Powering Plasma-Physics with RISC-V vector extension: the case of Vlasiator
Gerard Oliva Viñas (Barcelona Supercomputing Center)

The RISE Project: Advancing AI on RISC-V
Jeffrey Osier-Mixon (Red Hat)

Verification of a RISC-V system with multiple cores
Oscar Palomar (Barcelona Supercomputing Center)

Tackling Hardware Trojan Horses via Hardware-based Methodologies
Alessandro Palumbo (CentraleSupélec, Inria, Univ Rennes, CNRS, IRISA)

Detecting Microarchitectural Side-Channel Attacks via Hardware Security Checkers
Alessandro Palumbo (CentraleSupélec, Inria, Univ Rennes, CNRS, IRISA)

Accelerating software development for high performance compute using VDKs
Rae Parnmukh (Tenstorrent)

Snooper: A Flexible Tracing Solution for Fast Simulation and Analysis in RISC-V
Julian Pavon Rivera (Barcelona Supercomputing Center)

The Bicameral Cache: a split cache for RISC-V vector architectures
Borja Perez (Universidad de Cantabria)

GaZmusino: An extended edge RISC-V core with support for Bayesian Neural Networks
Samuel Perez Pedrajas (University of Zaragoza)

LEN5: an Out-Of-Order, Modular, Edge-Oriented RISC-V CPU
Vincenzo Petrolo (Politecnico di Torino)

Enabling RISC-V CI in Open-Source Projects: Challenges and Solutions
Marek Pikula (Samsung R&D Institute Poland)

AIA User Priority Mask Extension: Minimizing Critical Sections Side-Effects on Real-Time Automotive Systems
Sandro Pinto (University of Minho)

A Deep Dive into Integration Methodologies in RISC-V
Valeria Piscopo (Politecnico di Torino)

Towards an Industrial-Grade Open-Source FPU for RISC-V Vector Processors
Michael Platzer (Axelera AI)

Side-channel attack hardware detection module added to RISC-V core
Juliette Pottier (Nantes Université-IETR)

Open Challenges for a Production-ready Cloud Environment on top of RISC-V hardware
Guillem Prades (Barcelona Supercomputing Center)

Customized RISC-V In a Simple Game Console
Zdenek Prikryl (Codasip)

CVA6 RISC-V PMP Vulnerabilities against FIA
Kevin QUENEHERVE (Université Bretagne Sud - Lab-STICC (UMR 6285))

A Unified AI Accelerator Interface for Scalable RISC-V Architectures
Fucong Qiu (Institute of Computing Technology, Chinese Academy of Sciences)

Open-source SPMP-based CVA6 Virtualization
Manuel Rodríguez (Centro ALGORITMI/LASI)

RISCV-PySim: A Modular and Flexible Python-Based RISC-V Simulator
Carlos Rojas Morales (Barcelona Supercomputing Center)

Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis
Simon Rokicki (Irisa)

Who tests the TestRIG? Tooling for randomised tandem verification
Peter Rugg (University of Cambridge)

RIVeT-Co: Time-Predictable RISC-V based Vector Co-processor for High-Performance Computing
SONAM SINGH (Indraprastha Institute of Information Technology Delhi)

RISC-V Vector Extension. A Case Study on Time Series Analysis
Jose Sanchez-Yun (University of Málaga)

Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon
Philippe Sauter (IIS, ETH Zürich)

Learning by Puzzling: A Modular Approach to RISC-V Processor Design Education
Tobias Scheipel (Graz University of Technology)

FastISS RISC-V VP++: A Simulation Performance Evaluation of RVV Workloads
Manfred Schlaegl (Johannes Kepler University)

Prototyping custom RISC-V instructions with Seal5 and CoreDSL
Jan Schlamelcher (German Aerospace Center - Institute of Systems Engineering for Future Mobility)

RISC-V as an ASIP Platform for Portable Hearing Aid Devices
Sven Schönewald (Leibniz University Hanover - Institute of Microelectronic Systems)

Vectorization and Optimization of Gradient Boost Libraries for EUPilot VEC Chiplet
Muhammed Sen (AI4SEC OÜ)

Unified Emulation and Simulation Debug Environment for RISC-V Devices to Reduce Cost and Turnaround Time
Rejeesh Shaji Babu (Ashling Microsystems)

On a Static Analysis Methodology for Confidentiality and Security Signoff of RISC-V Crypto Core
Varun Sharma (Real Intent Inc.)

CHERI performance optimization
Carl Shaw (Codasip)

ProbRVCIM : Integrating Compute-in-Memory to RISC-V ISA for Probabilistic Learning and Inference at the Edge
Priyesh Shukla (Samsung Research / IIIT Hyderabad)

Software-Hardware Co-Verification for Traditional Verification Frameworks
Fangyuan Song (Institute of Computing Technology, Chinese Academy of Sciences)

Learning Computer Architecture with a Visual Simulation of RISC-V Processors
Esteban Stafford (Universidad de Cantabria)

Development of Fedora Linux Distribution for RISC-V (RV64G) Architecture
Billa Surendra (Centre For Development of Advanced Computing)

XiangShan Kunminghu V2: Architectural Innovations and Ecosystem Development of an Open-Source High-Performance RISC-V Processor
Haojin Tang (State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences)

Cloud-Based Binary Artifactory for RISC-V Software
Ali Tariq (10xEngineers)

Developing RISC-V Cores with Python
Rob Taylor (ChipFlow)

The Simulation-based Gold-Standard framework for verifying HDL branch predictors
Katy Thackray (University of Cambridge)

Performance and Co-Design Evaluation of RISC-V and Xilinx MicroBlaze V on ArtyA7-100T FPGA
Sravani Thota (guest)

Advanced Verification Suite for RISC-V Cores
Murat Tokez (ELECTRAIC)

The Eruption of RISC-V in HPC: Earth Sciences Codes on Long Vector Architectures
Pablo Vizcaino (Barcelona Supercomputing Center)

Virtual memory for real-time systems using hPMP
Konrad Walluszik (Infineon Technologies AG)

CHERI extended Muntjac SoC
Yuecheng Wang (University of Cambridge)

The Road to Making openEuler a RISC-V Server Platform Distro
Jingwei Wang (Institute of Software, Chinese Academy of Sciences)

RISC-V support implementation for ORC (Oil Runtime Compiler)
Filip Wasil (Samsung)

Reconfigurable Processor-Centric Accelerators for Safety-Critical Applications
Luis Waucquez (Centro Electronica Industrial - Universidad Politécnica de Madrid)

RISC-V VPU: A High-Performance Video Transcoding Card
Qian Wei (China Telecom Research Institute)

An interleaved multi-thread RISC-V design for SMP with dual core lockstep to support ASIL-D functional safety requirements
Jian Wei (ecarx)

RISC-V ISA with In-Memory Co-Processing Architecture for General-Purpose Computing
Bi Wu (Nanjing University of Aeronautics and Astronautics)

RISC-V CoVE implementation in priviliged firmware
Cui Xiaoxia (Alibaba)

UnityChip Verification: Scaling Out Hardware Verification with Software Testing Developers
Yunlong Xie (Institute of Computing Technology, CAS)

Finding More Bugs in Your RISC-V CPUs with DiffTest and XFUZZ
Yinan Xu (State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences)

An Architecture Design for Expressive Security
Jason Yu (National University of Singapore)

“One Student One Chip” Initiative: Learn to Build RISC-V Chips from Scratch with MOOC
Zihao Yu (ICT, CAS)

RISC-V Platform Firmware Implementation with UEFI and Its Future
Spike Yuan (Alibaba Damo Academy)

Hassert: Hardware Assertion-Based Agile Verification Framework with FPGA Acceleration
Ziqing Zhang (Institute of Computing Technology, CAS)

LLM-assisted Methodology for Embedded Software Performance Estimation on RISC-V
Weiyan Zhang (Researcher)

Kronos: A RVV-1.0 Short Vector Unit in Chisel
Jerry Zhao (UC Berkeley)

Optimizing Hardware for Neural Network Inference using Virtual Prototypes
Jan Zielasko (Cyber-Physical Systems, DFKI GmbH)

Co-simulation and architectural exploration with PolarFire SoC and Renode
Piotr Zierhoffer (Antmicro)

AccUnit: Accelerating Unit Level Verification for RISC-V Processors Using FPGA
weidong li (shanghaitech university)

Benchmarking TinyML CNN Kernels on RVV 1.0 Hardware: GCC 14 vs. LLVM 19
Philipp van Kempen (Technical University of Munich)

HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
yang zhong (Institute of Computing Technology Chinese Academy of Sciences)