Plenary sessions
Keynotes and presentations in the Gaston Berger amphitheatre (level -2)
Notes for plenary session presenters
Before the conference:
- Presenations shall be prepared as PPTX or PDF files.
- The final asbtract and slides are due for Monday, April 21st, 2025.
- At least one author of the poster must register for the core conference (Tuesday 13 to Thursday 15).
- The slides will be collected beforehand and displayed from a shared laptop.
Plenary sessions & Demos
Keynotes, invited talks, industrial and technical presentations will presented in plenary sessions in the Gaston Berger amphitheater. Demos will presented during lunches and some breaks in the Louis Armand East amphitheater
Tuesday 13, 09:00-10:30
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
Welcome to the RISC-V Summit Europe 2025 in Paris
T1.1.01, Tue 13 at 09:00, in Gaston Berger.
By Christian Fabre, RISC-V Summit Europe 2025 Local Chair, CEA.
Abstract: The welcome address to the RISC-V Summit Europe 2025 will present the venue, provide an overview of the agenda, and details the social event.
Program Overview of the RISC-V Summit Europe 2025
T1.1.02, Tue 13 at 09:05, in Gaston Berger.
By Borja Perez Paron, RISC-V Summit Europe 2025 Program Chair, Universidad de Cantabria.
Abstract: Details on the 3 days program, the CfP, the selected talks and the topcis covered.
RISC-V Technology Update
T1.1.03, Tue 13 at 09:15, in Gaston Berger.
By Andrea Gallo, RISC-V VP Technology, RISC-V.
(TBD)
T1.1.04, Tue 13 at 09:40, in Gaston Berger.
By Balaji Baktha, Founder, President, CEO, and Chairman, Ventana.
Abstract: (TBD)
Bio: Balaji Baktha is the founder and CEO of Ventana Micro Systems, a leader in high-performance RISC-V processors. He is an experienced semiconductor executive and a serial technology entrepreneur and investor with a proven track record in founding and exiting several successful startups over more than 30 years in Silicon Valley. Balaji is a board member of RISC-V International as well as several other startups, and a Limited Partner and Senior Advisor at PE and VC funds. Prior to Ventana, Balaji was the founder and CEO of Veloce Technologies, the world’s first 64-bit ARM based high performance processor for cloud-compute (acquired by AppliedMicro). Before Veloce, Balaji was the VP and GM of the Communications Business at Marvell Semiconductor where he managed multiple product groups including compute, wired and wireless networking, and Enterprise Storage SoCs. Before Marvell, Balaji co-founded Platys, a startup that pioneered iSCSI storage networking and was subsequently acquired by Adaptec (now Microsemi). Prior to Platys, Balaji founded Shuttle Technologies (acquired by SCM Micro) to build the first digital media & storage I/O SoCs for Apple, Sony, and HP.
Sovereignty, independence, innovation: 7 years of HW/SW codesign with RISC-V at CEA
T1.1.05, Tue 13 at 10:00, in Gaston Berger.
By Thomas Dombek, Head of Digital Integrated Circuits and Systems Department, CEA.
Abstract: By ending the epoch of closed, proprietary ISAs, RISC-V has opened a new era of innovation in the computing world. Its open ISA not only enables the tailoring of architecture to various application domains, from performance to low power, and from safety to security, but it also enables new forms of joint initiatives in the design and tools ecosystem. This ranges from new forums of cooperation between industrial competitors in the market, to new models of industry/academic collaboration. The versatility of open ISA specifications, which enables both open-source, public cooperation and also closed-door commercial agreements, will facilitate new kinds of partnerships and unexpected advances in the computing field at large. This talk will provide a return of experience from seven years of commitment to the RISC-V ecosystem and, a peek at key achievements of CEA and its academic and business partners.
Bio: Thomas Dombek is head of the Digital Systems and Integrated Circuits division at CEA LIST (French Atomic Energy Commission), Saclay, France. He received his master’s degrees in engineering from Ecole Centrale de Lyon, France, and in microelectronics from the Technical University of Darmstadt, Germany, in 1998. He has worked over 15 years in the semiconductor industry at various research and management positions within Philips, NXP and ST-Ericsson France. In 2011, he joined CEA LIST, heading research on software, modeling and hardware challenges in smart embedded systems.
Enabling the Next Phase of RISC-V: Product Innovation and Scalable Solutions
T1.1.06, Tue 13 at 10:15, in Gaston Berger.
By Ning He, SVP and CTO, Eswin.
Abstract: RISC-V has achieved remarkable success in the IoT application and is now expanding into more advanced scenarios. To sustain this growth, a comprehensive product portfolio, mature software support, and systematic large-scale deployments are essential. This presentation highlights how ESWIN Computing, a leading innovator in RISC-V, enriches the RISC-V ecosystem through multiple industry-first products while enhancing software capabilities. Additionally, we will showcase how our system-level solutions for vertical industries accelerate the structured adoption and widespread deployment of RISC-V, driving the ecosystem’s rapid evolution.
Bio: Dr. Ning He is the Senior Vice President and Chief Technology Officer of ESWIN Computing Technology Co. Ltd, a leading RISC-V products and solutions provider in China. He holds a Bachelor‘s and a Master’s degree from the University of Electronic Science and Technology of China, and a Ph.D. degree in Electrical Engineering from Arizona State University, USA. Prior to joining ESWIN, Dr. He served as Vice President and CTO at a company listed on China’s A-share market. With extensive expertise in modem system design, computing architecture, IC product solutions, and technology management, he now leads the development of RISC-V ecosystem and technology platforms at ESWIN. Beyond his corporate role, Dr. He actively contributes to industry standardization as the rotating chairman of both the RISC-V Working Committee at the China Electronics Standardization Association and the Zhongguancun Standardization Association, driving the standardization and advancement of RISC-V technologies.
Tuesday 13, 11:30-13:00
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
RISC-V State of the Union
T1.3.01, Tue 13 at 11:30, in Gaston Berger.
By Krste Asanović, Chief Architect, SiFive.
Abstract: In this session RISC-V’s Chief Architect will give an overview of RISC-V adoption across computing markets from Embedded to AI. Krste will discuss new developments in the RISC-V ISA, including security extensions and matrix extensions for AI, as well as new profile and platform initiatives.
Bio: Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-V ISA project at UC Berkeley, serves as chairman of RISC-V International, and cofounded SiFive Inc. to support commercial use of RISC-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.
RISC-V ISA Extensions with Hardware Acceleration for Hyperdimensional Computing
T1.3.02 (sub. #109), Tue 13 at 12:00, in Gaston Berger.
By Rocco Martino, Sapienza University of Rome. Marco Angioli, Sapienza University of Rome. Antonello Rosato, Sapienza University of Rome. Marcello Barbirotta, Sapienza University of Rome. Abdallah Cheikh, Sapienza University of Rome. Mauro Olivieri, Sapienza University of Rome.
Abstract: Hyperdimensional Computing (HDC) leverages high-dimensional distributed representations called hypervectors (HVs) and simple arithmetic operations, making it an ideal paradigm for learning tasks on resource-constrained devices. This work introduces the first RISC-V Instruction Set Architecture (ISA) extension specifically designed to execute all fundamental arithmetic operations of HDC directly through dedicated instructions, which, when appropriately combined, enable a variety of learning tasks by efficiently encoding and processing information. This extension is coupled with a specialized hardware acceleration unit, integrated into the Klessydra-T03 RISC-V core, to perform computations on binary HVs efficiently. The proposed solution enables a seamless trade-off between execution time and hardware resource utilization through both synthesis-time configurability and runtime programmability. The custom ISA extension is fully integrated into the RISC-V GCC toolchain, allowing software developers to exploit its capabilities via intrinsic function calls. Benchmarking on an FPGA platform demonstrates significant performance improvements across a wide range of HDC tasks, from basic arithmetic operations to real-world classification problems.
Real-Time Extension to the RISC-V Advanced Interrupt Architecture
T1.3.03 (sub. #206), Tue 13 at 12:15, in Gaston Berger.
By Alexey Khomich, Synopsys Inc. Evgenii Paltsev, Synopsys. Paul Stravers, Synopsys Inc.
Abstract: The Real-Time Interrupt Architecture (RTIA) is the evolution of RISC-V Advanced Interrupt Architecture (AIA) targeted to extend use cases to real-time latency critical scenarios and/or to resource constrained designs. The RTIA defines necessary mechanisms for interrupt nesting and low latency fixed overhead interrupt handling. Keeping compatibility with RISC-V Privileged ISA and RISC-V AIA, the RTIA provides the same programming model for light weight embedded applications and heavy feature rich systems allowing mixing it in virtual environments.
RISC-V Heterogeneous Computing Paradigm: Atomic IO Enqueue Extension and Virtualization
T1.3.04 (sub. #148), Tue 13 at 12:30, in Gaston Berger.
By Ren Guo, Alibaba Damo Academy.
Abstract: With the increasing diversification of intelligent computing workloads, traditional programming paradigms face multidimensional challenges driven by architectural innovations. Addressing the concurrent demands of heterogeneous tasks, including AI inference, real-time graphics rendering, and high-performance signal processing, this presentation focuses on atomic IO enqueue instructions - the core technology enabling hardware accelerator interactions in heterogeneous computing architectures. This approach establishes efficient accelerator communication mechanisms through hardware primitives such as 64-byte atomic enqueue transfers and queue status feedback. At the protocol level, PCIe specifications define DMWr TLP (Transaction Layer Packet) for non-post write operations, while Armv8.7/9.2 implements 64-byte atomic enqueue operations via ST64BV instructions, and x86 architectures provide comparable functionality through MOVDIR64B and ENQCMD(S) instructions.
This presentation introduces RISC-V’s Atomic IO Enqueue Extension (AIOE) and its virtualization enhancements: the G-stage Page Table In-Process Context (GIPC) mechanism for RISC-V IOMMU, which improves accelerator sharing work queue in multi-tenant environments. In addition, we will share AIOE’s latency mitigation approach for PCI-e.
Accelerating AI Models with Andes Matrix Multiplication (AMM) and RISC-V Vector (RVV) extensions: From CNNs to LLMs
T1.3.05 (sub. #86), Tue 13 at 12:45, in Gaston Berger.
By Pei-Hsiang Hung, Andes Technology. Chung-Hua Yen, Andes Technology. I-WEI WU, Andes Technology.
Abstract: Matrix multiplication is a critical operation in a wide range of compute-intensive applications, including machine learning, image processing, and scientific computing. The computational demands of large-scale matrix operations necessitate specialized hardware acceleration to improve efficiency and performance. To address this challenge, RISC-V International (RVI) formed the Integrated Matrix Extension (IME) Task Group. To serve immediate market demands, Andes Technology implements the Andes Matrix Multiplication (AMM) instruction set, an extension to the RISC-V Vector Extension (RVV), which Andes presented in IME meetings. The AMM instruction set introduces two primary enhancements:
- Matrix operations optimized for 8-bit integers, specifically targeting AI and deep learning applications
- Advanced 2D load/store instructions that minimize memory access overhead
To assess AMM’s capabilities, we integrated it into the Intermediate Representation Execution Environment (IREE) for efficient compilation and execution on AMM-enabled RISC-V systems. A key aspect of this implementation involved extending IREE’s compilation infrastructure, which included:
- Developing a new MLIR pass to tensorize matrix multiplication and tensor data load/store operations
- Designing a custom MLIR dialect tailored for AMM to support all its instructions.
- Implementing conversion passes to lower matrix multiplication and tensor operations from the vector dialect to AMM one
Our evaluation covered a broad spectrum of AI models, ranging from convolutional neural networks (CNNs) to large language models (LLMs), to measure performance improvements. This presentation explores the integration process, shares benchmark results, and discusses strategies for optimizing AI workloads using AMM and RISC-V Vector Extensions. We also examine the challenges encountered during AI model compilation and consider future developments in RISC-V-based AI acceleration.
Tuesday 13, 13:00-14:30
Demos in Louis Armand East amphitheater (level -3).
Booths and posters in expo area's 3 levels.
Tuesday 13, 14:30-15:30
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
The Custom Silicon Imperative: Addressing Manufacturing and Supply Chain Realities
T1.5.01, Tue 13 at 14:30, in Gaston Berger.
By Pablo Valerio, Supply Chain section Editor, EETimes.
Abstract: The semiconductor industry faces creative disruption due to the rise of bespoke silicon driven by demands for AI and high-performance computing, where RISC based cores are displacing traditional stakeholders. This trend presents manufacturing and supply chain challenges due to the cost of development and the complexity of international supply chains. Open-source architectures like RISC-V are gaining traction as an alternative, offering customization and potentially reducing reliance on unstable supply chains, particularly in Europe.
Bio: Pablo Valerio is a seasoned engineer with 30+ years of experience. For over 10 years, he has been a contributing editor and analyst for EE Times (where he edits the Supply Chain section). He also wrote for EPSNews, InformationWeek, EBN, LightReading, Network Computing, and IEEE Xplore. His coverage spans Supply Chain, Semiconductors, Networks, IoT, Security, and Smart Cities. He holds an MEng, Electrical and Electronics Engineering from The Ohio State University.
Akeana, leveraging strong legacy to offer the broadest IP portfolio
T1.5.02, Tue 13 at 14:45, in Gaston Berger.
By Graham Wilson, Head of Product, Akeana.
Abstract: A history lesson on the evolution of the team that formed Akeana as an industry leader of processor and interconnect IP, allowing them to build and verify a broad range of processor IP.
Bio: Graham has over 25 years of experience in the semiconductor, IP industry with 15 years in processor IP, working at companies as Tensilica/Cadence, Synopsys and SiFive. His main area of focus has been DSP, Vector processors, with recent focus on AI computation processors. At Akeana, Graham is responsible for product management and product marketing.
Enter the RISC-V AI era with Andes
T1.5.03, Tue 13 at 14:47, in Gaston Berger.
By Niraj Dengale, Senior FAE, Andes Technology.
Abstract: Andes has been a pioneer in enabling customers to achieve their AI processing needs through providing both hardware and software solutions. My talk will shade a light on how efficiently Andes is supporting the AI ecosystem.
Bio: Niraj Dengale working as a senior FAE in Andes Technology Europe Munich office to help our customers during the CPU evaluation process as well as after they start SoC integration. Niraj have been in Andes for 7 years and witnessed the impact RISC-V is making in the CPU market.
Getting towards first-time RISC-V silicon with automated end-to-end formal
T1.5.04, Tue 13 at 14:49, in Gaston Berger.
By Ashish Darbari, Founder & CEO, Axiomise.
Abstract: This talk will share how our smart formal methods powered by formalISA® and footprintTM can empower you to build your RISC-V silicon right the first time, going beyond compliance testing by axiomising correctness through exhaustive proofs, exposing corner-case bugs and coverage for functional, PPA, safety and security verification.
Bio: As CEO of Axiomise, Dr Ashish Darbari co-founded and led Axiomise in successfully deploying the unique combination of training, consulting, services, custom solutions, and verification IP. Under his leadership, Axiomise acquired over 20 customers in 7+ years with zero VC funding and turned Axiomise into a multi-million-pound organisation with a team of 25 staff members. Ashish holds a Bachelor’s in EEE from BIT Mesra, India, a Master’s from TU Dresden, Germany and a DPhil in Computer Science from the University of Oxford, focusing on formal verification. Before starting Axiomise, Ashish worked in OneSpin Solutions, Imagination Technologies, General Motors, Arm and Intel.Ashish is a Fellow of the British Computing Society and a senior member of IEEE and ACM. From 2015-1018, he was a Royal Academy of Engineering Visiting Professor at the University of Southampton. A keen innovator in formal verification, Ashish has 67 US, UK and EU patents in formal verification.
Revolutionizing RISC-V Chip Design with AI Agents
T1.5.05, Tue 13 at 14:51, in Gaston Berger.
By David Wang, Founding Engineer, ChipAgents.ai.
Abstract: ChipAgents introduces the world’s first AI agent tailored for chip design and verification. This innovative tool leverages large language models to automate and enhance RTL development, debugging, and verification processes. By integrating AI agents into the RISC-V design workflow, ChipAgents significantly accelerates time-to-market and improves design accuracy. This talk will explore how AI-driven methodologies are transforming traditional semiconductor design paradigms, offering insights into the future of AI-assisted hardware engineering.
Bio: David Wang is a Founding Engineer at ChipAgents and an AI researcher at UCSB’s NLP Lab, where he has worked on iterative optimization of language model output and synthetic data generation. His expertise spans machine learning, NLP, and distributed systems, with experience at GlossGenius, Snowflake, C3.AI, and Viasat.
What’s new at Codasip?
T1.5.06, Tue 13 at 14:53, in Gaston Berger.
By Peter Shields, Senior Product Manager, Codasip.
Abstract: As the leading European RISC-V vendor, we have a lot going on. This talk will share our latest product updates including new possibilities for fast migration from Arm to RISC-V, new core customization features, and the latest progress in CHERI memory protection. We will also talk about our advancements in high-performance computing as part of the EU-funded DARE project.
Bio: Peter Shields is a Product Manager at Codasip. He has over 25 years of experience in Applications Engineering, Engineering Management and Customer Engineering roles in both EDA and semiconductor IP, particularly for complex SoCs. Prior to Codasip, Peter was a product manager at Siemens, and previously held roles at UltraSoC, Synopsys, Imagination Technologies, Mentor, LogicVision and Cadence. He holds a BEng from the University of Birmingham, UK.
Real-Time Trace: The Key to Streamlined Embedded System Development and Validation
T1.5.08, Tue 13 at 14:57, in Gaston Berger.
By Soufian Elmajdoub, Country Manager LAUTERBACH France, Lauterbach.
Abstract: This lightning talk demonstrates how real-time trace technology significantly accelerates embedded system development cycles on RISC-V platforms. We’ll showcase how our JTAG debug tools provide developers with unprecedented visibility into system behavior, enabling faster troubleshooting, more efficient validation processes, and reduced time-to-market.
Bio: Soufian El-Majdoub leads Lauterbach operations in France as Country Manager. With significant experience in the semiconductor industry, he previously held positions at STMicroelectronics and NXP. His technical expertise covers embedded systems, debugging technologies, ARM architectures, embedded Linux, and microcontroller environments, giving him a perfect understanding of the challenges and opportunities in the RISC-V ecosystem. Based in the Paris region, Soufian combines deep technical understanding with business development skills, allowing him to bridge the gap between Lauterbach’s complex debugging solutions and customer needs in the growing RISC-V ecosystem.
The LLVM Universe Project: What We Learned from openEuler RISC-V
T1.5.09, Tue 13 at 14:59, in Gaston Berger.
By Jingwei Wang, Engineer of the Institute of Software, Chinese Academy of Sciences, OpenEuler.
Abstract: The LLVM Parallel Universe Project for openEuler is an ambitious exploratory effort to gradually transition openEuler and its broad software ecosystem from GCC to LLVM-based toolchains. Initiated by the Institute of Software, Chinese Academy of Sciences (ISCAS) and Huawei Compiler Lab, the project focuses on the RISC-V architecture while maintaining full compatibility with openEuler’s official codebase, release cycles, and quality standards.By the time of the openEuler 25.03 release, the project had moved to an RVA22 compiler baseline, with support for the Vector extension already activated.
Bio: A member of the openEuler Technical Committee responsible for maintaining the RISC-V SIG, and a participant in the RISC-V Advocate Program, dedicated to strengthening the RISC-V ecosystem within the openEuler community.
Semidynamics, NPU chip architecture reinvented for ultra-powerful AI with zero latency
T1.5.10, Tue 13 at 15:01, in Gaston Berger.
By Volker Politz, CSO, Semidynamics.
Abstract: Semidynamics is revolutionizing NPU with a single RISC-V ISA AI solution. Discover the solutions that we offer and how they can help you in your projects.
Bio: Volker Politz is the Chief Sales officer at Semidynamics, responsible for all IP sales and business development activities as well as product marketing. Prior to this, he was VP sales at Roviero, an AI IP start-up in California, held EU Sales and Global Auto Business management positions in Verisilicon and worked as IP sales manager in Synopsys Europe. He was Vice President of Product and Segment Marketing at Imagination Technologies. He is an international marketing, business development and management executive with over 30 years’ experience in semiconductor and technology companies. He also held roles and responsibilities in Europe, Asia and the United States with experience built from engineering, marketing, sales, and general management positions at Hitachi and Renesas. He has broad know-how in vertical domains such as digital multimedia, broadcast technologies, automotive, industrial, mobile, security and AI. Volker holds a Masters engineering degree in communication electronics from Fachhochschule Konstanz, Germany and an MBA from Open University, United Kingdom.
The RISC-V momentum continues.
T1.5.11, Tue 13 at 15:03, in Gaston Berger.
By Manfred Schlett, Senior Director, SiFive.
Abstract: SiFive will highlight our latest progress in embedded and automotive applications, showcasing how we are driving innovation.
Bio: As SiFive’s Business Director for Automotive, Manfred’s background encompasses executive roles at Automotive Tier 1 suppliers, as well as business and technical leadership across prominent semiconductor companies like Qualcomm, Cambridge Silicon Radio, and Renesas, and innovative startups such as Hyperstone. His Ph.D. in Mathematics complements an exhaustive track record in the design of microprocessors and related platforms.
Tuesday 13, 15:30-16:30
Demos in Louis Armand East amphitheater (level -3).
Booths and posters in expo area's 3 levels.
Tuesday 13, 16:30-18:00
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE
T1.7.01 (sub. #99), Tue 13 at 16:30, in Gaston Berger.
By Adeel Ahmad, 10xEngineers. Nouman Amir, 10xEngineers. Ahmad Tameem Kamal, 10xEngineers. Bilal Zafar, 10xEngineers.
Abstract: This project aims to enable RISC-V microkernel support in the IREE Machine Learning Compiler. It includes enabling the lowering of the MLIR operations to IREE microkernel calls and implementing microkernel functions for RISC-V. A comprehensive analysis of RISC-V ISA would also be provided as part of the project to identify areas where it lags behind x86 and ARM when targeting GenAI models. This project is a work in progress, and hence, the proposed methodology is discussed in the extended abstract. We aim to improve the RISC-V software ecosystem and spark community interest in expanding RISC-V support in ML compilers and kernel libraries.
Unlocking Performance, Profit, and Compliance: The RISC-V Approach to Medical AI
T1.7.02 (sub. #170), Tue 13 at 16:45, in Gaston Berger.
By Raja Gopal Hari Vijay Sitharaman, Zoho Corporation.
Abstract: Medical AI applications—including diagnostics, predictive analytics, and robotic surgery—demand specialized processing capabilities and must meet stringent performance requirements. However, in medical AI commercialization, meeting these demands is only part of the challenge. A critical hurdle is ensuring compliance with stringent regulatory standards such as FDA (U.S.), CE (Europe), and MDR (Medical Device Regulation), while maintaining innovation, efficiency, and cost-effectiveness. Traditional, some proprietary architecture often present significant barriers to achieving this balance. In contrast, RISC-V, with its open-source, modular ISA design, offers a key to unlocking this potential and fosters open collaboration, accelerating AI-specific optimizations across diverse applications. Its flexibility allows for tailored AI acceleration and secure computing – leading to, for example, significantly faster image processing times in diagnostic imaging or lower latency in real-time. This and verifiable regulatory compliance across hardware, operating systems, and software stacks of the RISC-V ecosystem, lower entry barriers and increase profitability by reducing development costs and speeding up time-to-market. This paper explores how RISC-V’s open ecosystem supports regulatory adherence, drives AI-optimized medical solutions, and unlocks new opportunities for scalable, secure, and cost-effective AI-driven healthcare innovations.
Flex-RV: World’s First Non-silicon RISC-V Microprocessor
T1.7.03 (sub. #23), Tue 13 at 17:00, in Gaston Berger.
By Emre Ozer, Pragmatic. Jedrzej Kufel, Pragmatic Semiconductor. Shvetank Prakash, Harvard University. Alireza Raisiardali, Pragmatic Semiconductor LTD, KU Leuven. Olof Kindgren, Qamcom. Ronald Wong, Pragmatic Semiconductor. Nelson Ng, Pragmatic Semiconductor. Damien Jausseran, Pragmatic Semiconductor. Feras Alkhalil, Pragmatic Semiconductor. David Kong, Harvard University. Gage Hills, Harvard University. Richard Price, Pragmatic Semiconductor. Vijay Janapa Reddi, Harvard University.
Abstract: We present, Flex-RV, a 32-bit microprocessor based on RISC-V instruction set fabricated with Indium-Gallium-Zinc-Oxide (IGZO) thin-film transistors (TFTs) on a flexible substrate, enabling an ultra-low-cost bendable microprocessor, which makes the World’s first non-silicon RISC-V microprocessor. Flex-RV integrates a programmable machine learning (ML) hardware accelerator, and demonstrates new instructions to extend the RISC-V instruction set to run ML workloads. It is implemented, fabricated and demonstrated to operate at 60 kHz consuming less than 6 mW power and its functionality when assembled onto a flexible printed circuit board is validated whilst executing programs under flat and tight bending conditions. Flex-RV pioneers an era of ultra low-cost open standard non-silicon 32-bit microprocessors for applications at Extreme Edge.
Wednesday 14, 08:00-09:00
Community breakfast in Louis Armand amphitheater (level -3).
Wednesday 14, 09:00-10:30
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
A cloud first: Scaleway’s RISC-V servers
T2.1.01, Wed 14 at 09:00, in Gaston Berger.
By Fabien Piuzzi, Scaleway.
Enhancing your RISC-V SoC debug and optimization with embedded functional monitors
T2.1.02, Wed 14 at 09:30, in Gaston Berger.
By Mat O’Donnell, Software Architect Lead, Siemens.
Abstract: A modern RISC-V SoC may have up to several thousand embedded processor cores, running highly optimized software workloads in the field. Time-to-market pressures, system performance and in-field reliability requirements drive a need for high visibility into large fleets of deployed devices executing real-life software workloads. Traditional debug solutions are typically not built for the complexity seen in today’s complex SoCs. In this presentation, we will explain how a scalable system of embedded functional monitors combined with embedded and host/cloud based analytic software can provide actionable data and insights that helps debug, validate, and optimize RISC-V SoC devices and systems from lab bring-up to reliable large scale deployment.
Bio: Mat O’Donnell is a Software Architect Tech Lead at Tessent Embedded Analytics, Siemens EDA. Mat has 25 years of experience working in the Software Industry across multiple successful startups. In March 2017 Mat joined Tessent Embedded Analytics providing software solutions for its embedded silicon IPs where he leads a team of engineers specializing in efficient host-based software support for functional monitoring.
XiangShan KMHv2: An Open Source RISC-V Core with >15/GHz for SPECCPU2006
T2.1.03, Wed 14 at 09:45, in Gaston Berger.
By Yungang Bao, Deputy director of ICT/CAS and Chief Scientist of Beijing Institute of Open Source Chip , BOSC.
Abstract: Xiangshan is an open-source high-performance RISC-V core that was initiated in 2020 (https://github.com/OpenXiangShan/XiangShan). After five years of development, Xiangshan has undergone three architectural upgrades and four tape-outs, all of which have met the expected performance targets. Currently, the latest generation of Xiangshan KMHv2, has completed its RTL design and verification, achieving a performance score of 15/GHz for SPECCPU2006, with comprehensive performance close to that of ARM Neoverse N2. It has already been delivered to companies for SoC development. Notably, not only is the RTL codes of Xiangshan itself open-source, but a series of development and verification tools are also open-source. More information will be introduced in the talk.
Bio: Yungang Bao is a professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the deputy director of ICT, CAS. Prof. Bao founded China RSIC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture and computer systems. He is leading the XiangShan project (https://github.com/OpenXiangShan/XiangShan), which aims to build an open-source high performance RISC-V core. He launched the One Student One Chip (OSOC) Initiative in 2019. His work was published on top conferences and journals such as ASPLOS, Communication of the ACM, HPCA, ISCA, MICRO etc. and was selected to IEEE Micro Top Picks. He was the winner of CCF-Intel Young Faculty Award of the year for 2013 and the winner of CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.
Beyond Innovation: RISC-V’s Path to Mass Adoption with Mature IP.
T2.1.04, Wed 14 at 10:00, in Gaston Berger.
By Wei-Han Lien, Chief Architect and Senior Fellow, Tenstorrent.
Bio: Wei-Han Lien is a Chief Architect and Senior Fellow in Machine Learning hardware architecture. He is currently leading an architecture team in defining a high-performance RISC-V CPU, fabric, system caching, and high performance memory subsystem for the Tenstorrent heterogeneous high-performance computation platform for AI and HPC computing. He is also leading the definition of Tenstorrent’s chiplet architecture for constructing scalable, configurable, and composable SiP with cohesive power management, security, and system management architectural definitions for compatibility. Before joining Tenstorrent, Wei-Han joined Apple through the PA Semi acquisition. He led Apple design team on the microarchitectural definitions of two of the most transformative Apple iPhone/iPad application processors from scratch, the A6 and A7 CPU projects. The Apple A7 CPU core is a solid CPU microarchitecture substrate for future generations of A-series (A7-A14) iPhone/iPad mobile processors and M-series (M1) MacBookPro processors. Before Apple, he was a distinguished architect leading P.A.Semi’s PWRficient PA6T dual O-o-O triple-issue superscalar PowerPC CPU cores. At Raza Microelectronics, he led the microarchitectures of the single-chip 40Gb scalable shared-memory switching chip and distributed-shared-memory cache coherent Ethernet switch. He joined Nexgen and AMD after graduating from the University of Michigan; he was part of a team designing the Nx586 (AMD K6), the most competitive microprocessor product to the Intel Pentium processor from 1997-1999 in the market.
The case for Open Source Hardware at Thales: Motivations and Recent Miletones with CVA6
T2.1.05, Wed 14 at 10:15, in Gaston Berger.
By Bernhard Quendt, Chief Technical Officer Thales Group, Thales.
Abstract: ( need more time)
Bio: Dr. Bernhard Quendt holds engineering degrees from the University of Stuttgart and Télécom Paris (ENST), and completed a PhD at the Technical University of Munich, where he was awarded the Rohde & Schwarz Prize. Formerly Chief Technical Officer for Siemens Digital Industries, Dr. Bernhard Quendt joined the Siemens Communications division in 1999 before being appointed Vice President R&D for Siemens Rail Automation in 2005. In 2011 he took the responsibility for platform activities and R&D as Vice President for Siemens Industrial Automation Systems and since 2015, he held the position of the Chief Technical Officer at Siemens Digital Industries. Bernhard Quendt joined Thales in 2020 as Chief Technical Officer and Senior Vice President.
Wednesday 14, 10:30-11:30
Demos in Louis Armand East amphitheater (level -3).
Booths and posters in expo area's 3 levels.
Wednesday 14, 11:30-13:00
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
A Safe Software Convergence: How Automotive and Industrial Designs are Eliminating Boundaries and Creating Opportunities
T2.3.01, Wed 14 at 11:30, in Gaston Berger.
By Edward Wilford, Senior Research Manager, Omdia.
Abstract: For decades, the automotive sector has been considered something of an island, with a high moat and a unique development cycle. However, in recent years and spurred mainly by a rich crop of new entrants from China, automotive technology has accelerated and broadened. A new focus on more general-purpose compute, driven by a software-first approach, has as an unintended but beneficial consequence opened up the barriers between automotive and industrial applications, and paved the way for product development shaped more by function than application. This talk will demonstrate that the various software-defined system revolutions are in fact a single phenomenon happening across industries, anywhere where advanced edge deployments are on the rise. Furthermore, why this presents itself as a unique opportunity for RISC-V will be discussed.
Bio: Edward is the Senior Research Director, Automotive, at Wards Intelligence and Omdia Automotive, having previously covered automotive AI and semiconductors as Omdia’s Senior Principal Analyst, IoT. He has written extensively on embedded applications processors, edge AI, advanced connectivity, and novel semiconductor architectures such as RISC-V. He started in the industry in 2016 when he joined Arm as a market intelligence analyst, leading market research and forecasting in the automotive and IoT division. He has also worked in financial services and media roles in London. He has a BA from Durham University and an MPhil in Linguistics from the University of Cambridge.
Exhaustive Security Verification of CHERI Processors
T2.3.02 (sub. #63), Wed 14 at 11:45, in Gaston Berger.
By Anna Lena Duque Antón, RPTU Kaiserslautern-Landau. Johannes Müller, RPTU Kaiserslautern-Landau. Philipp Schmitz, RPTU Kaiserslautern-Landau. Tobias Jauch, RPTU Kaiserslautern-Landau. Alex Wezel, RPTU Kaiserslautern-Landau. Lucas Deutschmann, RPTU Kaiserslautern-Landau. Mohammed R. Fadiheh, Stanford University. Dominik Stoffel, RPTU Kaiserslautern-Landau. Wolfgang Kunz, RPTU Kaiserslautern-Landau.
Abstract: CHERI is a promising approach to safeguarding data in memory by providing and enforcing fine-grained memory protection directly in hardware. The recently published VeriCHERI verification flow can verify global confidentiality and integrity properties for CHERI systems “spec-free”, i.e., without relying on a golden ISA model. We present a case study to demonstrate the effectiveness and scalability of VeriCHERI on the CHERIoT Ibex RISC-V processor.
The RISE Project: Advancing RISC-V Software
T2.3.03 (sub. #171), Wed 14 at 12:00, in Gaston Berger.
By Nathan Egge, Google. Ludovic Henry, Rivos.
Abstract: The RISC-V Software Ecosystem (RISE) Project is in high gear investing time and money on software to support RISC-V, including more than $500K on contracts for further enhancements. This talk will highlight the way RISE prioritizes projects, and will outline some of our key achievements in the past year.
We have many ideas for further development and investments in 2025. Please join us for a deep dive into the latest developments shaping the RISC-V software ecosystem.
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
T2.3.04 (sub. #186), Wed 14 at 12:15, in Gaston Berger.
By Riccardo Tedeschi, University of Bologna. Gianmarco Ottavi, University of Bologna. Nils Wistoff, ETH Zurich. Zexin Fu, ETH Zurich. Filippo Grillotti, STMicroelectronics. Fabio De Ambroggi, STMicroelectronics. Elio Guidetti, STMicroelectronics. César Fuguet, Univ. Grenoble Alpes, Inria. Luca Benini, ETH Zurich, University of Bologna. Davide Rossi, University of Bologna.
Abstract: Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on the industry-supported open-source CVA6 core and its superscalar variant, CVA6S, we introduce CVA6S+, an enhanced version incorporating improved branch prediction, register renaming and enhanced operand forwarding. These optimizations enable CVA6S+ to achieve a 43.5% performance improvement over the scalar configuration and 10.9% over CVA6S, with an area overhead of just 9.30% over the scalar core (CVA6). Furthermore, we integrate CVA6S+ with the OpenHW Core-V High-Performance L1 Dcache (HPDCache) and report a 74.1% bandwidth improvement over the legacy CVA6 cache subsystem.
A RISC-V based accelerator for Post Quantum Cryptography
T2.3.05 (sub. #112), Wed 14 at 12:30, in Gaston Berger.
By Ambily Suresh, Silicon Austria Labs. Andrew Wilson, Silicon Austria Labs. Diego Gigena-Ivanovich, Silicon Austria Labs. Manuel Freiberger, Silicon Austria Labs. Willibald Krenn, Silicon Austria Labs.
Abstract: Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware and software implementations to perform at optimum efficiency. We present our ongoing work on the implementation of RISC-V based accelerators for PQC algorithms, in particular the Classic McEliece Key Encapsulation Mechanism. Our system includes a PQC accelerator and an Open-HW Group CVA-6 core along with a PQC-specific instruction set. This presentation describes the architecture, performance estimates, and demonstration plans in the future.
Implementing Runtime-Configurable Endianness in RISC-V: Challenges and Solutions
T2.3.06 (sub. #105), Wed 14 at 12:45, in Gaston Berger.
By Lawrence Hunter, Codethink. Roan Richmond, Codethink. Ben Dooks, Codethink.
Abstract: The RISC-V Privileged Specification introduced dynamic endianness switching in version 1.12, though no commercial hardware yet supports it. This work extends QEMU to enable big-endian execution, allowing the booting of a big-endian Linux system with OpenSBI. Modifications were required across QEMU, OpenSBI, the Linux kernel, and supporting libraries to ensure correct memory operations, instruction encoding, and runtime patching. The project demonstrates the feasibility of big-endian support for RISC-V, providing a foundation for future hardware and software development.
Wednesday 14, 13:00-14:30
Demos in Louis Armand East amphitheater (level -3).
Booths and posters in expo area's 3 levels.
Wednesday 14, 14:30-15:30
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
RISC-V: Powering the Future of High Performance Computing?
T2.5.01, Wed 14 at 14:30, in Gaston Berger.
By Nick Brown, Senior Research Fellow, ECC.
Abstract: For all it’s successes in embedded computing, RISC-V is yet to become mainstream in High Performance Computing (HPC). However, times are changing and at the same time that RISC-V is making progress towards more high end usage, the HPC community is facing unprecedented challenges around meeting the demand for increased performance but in a more sustainable manner. RISC-V has an opportunity to displace entrenched technologies here, and in this talk I will highlight the key benefits that RISC-V can provide to HPC, describe some of the important activities and early achievements in this area, and identify critical missing pieces that we as the RISC-V community should look to prioritise.
Bio: I am interested in the role that novel hardware can play in future supercomputers, and am specifically motivated by the grand-challenge of how we can ensure scientific programmers are able to effectively exploit such technologies without extensive hardware/architecture expertise. My research combines novel algorithmic techniques for this new hardware, programming language & library design, and compilers. I coordinate knowledge exchange for the ExCALIBUR exascale software programme, and chair the RISC-V International HPC SIG. I head up EPCC’s PhD programme and am course organiser for the in-person and online Parallel Design Patterns MSc modules. I am currently undertaking a Royal Society of Edinburgh personal research fellowship.
From Open Silicon to Sovereign Supercomputing: EuroHPC’s Vision for RISC-V
T2.5.02, Wed 14 at 14:45, in Gaston Berger.
By Alexandra Kourfali, Program Manager, EuroHPC.
Abstract: The EuroHPC Joint Undertaking is transforming Europe’s supercomputing landscape. EuroHPC initiatives aim to facilitate open-source HPC innovation using HW/SW co-design, advanced nodes, and cutting-edge technologies. Central to this vision lay two flagship EuroHPC initiatives focused on developing high-performance RISC-V processors and accelerators. RISC-V is uniquely positioned to power the next generation of HPC systems, as an open and extensible instruction set architecture. This talk will explore how the RISC-V ISA and the EuroHPC flagships are laying the groundwork for a new class of European supercomputers — energy-efficient, scalable, sovereign, and built for the future.
Bio: Alexandra Kourfali is a program manager of research and innovation at the EuroHPC Joint Undertaking. She received her Computer Engineering diploma from the University of Thessaly, Greece, and her Ph.D. in Computer Engineering from Ghent University, Belgium. She has worked in research, development, and innovation for a decade in academia and the private sector in Belgium, the Netherlands, Spain, Germany, and Luxembourg. Her research experience ranges from HPC, reconfigurable, and approximate computing to hardware reliability and computer architectures. Since she joined EuroHPC, she has been managing the chips projects with a strong focus on the RISC-V initiatives
Monte Cimone v2: Down the Road of RISC-V High-Performance Computers
T2.5.03 (sub. #177), Wed 14 at 15:00, in Gaston Berger.
By Emanuele Venieri, University of Bologna. Simone Manoni, University of Bologna. Giacomo Madella, University of Bologna. Federico Ficarelli, CINECA. Daniele Gregori, E4 Computer Engineering SpA. Daniele Cesarini, CINECA. Luca Benini, University of Bologna. Andrea Bartolini, University of Bologna.
Abstract: Many RISC-V platforms and SoCs have been announced in recent years targeting the HPC sector, but only a few of them are commercially available and engineered to fit the HPC requirements. The Monte Cimone project targeted assessing their capabilities and maturity, aiming to make RISC-V a competitive choice when building a datacenter. Nowadays, RV SoCs with vector extension, form factor and memory capacity suitable for HPC applications are available in the market, but it is unclear how compilers and open-source libraries can take advantage of its performance. In this paper, we describe the performance assessment of the upgrade of the Monte Cimone (MCv2) cluster with the Sophgo SG2042 processor’s HPC operations. The upgrade increases the attained node’s performance by 127x on HPL DP FLOP/s and 69x on Stream Memory Bandwidth.
Ahead of Time Generation for GPSA Protection in RISC-V Embedded Cores
T2.5.04 (sub. #124), Wed 14 at 15:15, in Gaston Berger.
By Louis Savary, Inria. Simon Rokicki, Irisa. Steven Derrien, Université de Bretagne Occidentale/Lab-STICC. Erven Rohou, Inria.
Abstract: State-of-the-art hardware countermeasures against fault attacks are based, among others, on control flow and code integrity checking. These integrities can be asserted by Generalized Path Signature Analysis and Continuous Signature Monitoring. However, supporting such mechanisms requires a dedicated compiler flow and does not support indirect jumps. In this work we propose a technique based on a hardware/software runtime to generate those signatures while executing unmodified COTS RISC-V binaries. The proposed approach has been implemented on a pipelined rv32i processor, and experimental results show an average slowdown of x1.82 compared to unprotected implementations while being completely compiler independent.
Wednesday 14, 16:30-18:00
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
Chips JU and the Vehicle of the Future – a RISC V view
T2.7.01, Wed 14 at 16:30, in Gaston Berger.
By Georgi Kuzmanov, Senior Programme Officer, Chips JU.
Abstract: The Chips Joint Undertaking (JU) was established in September, 2023, to implement the Chips for Europe Initiative, the first pillar of the European Chips Act and to continue the missions of its preceding joint technology initiatives in the field of electronic components and systems (ECS). For several years now, the Chips JU has been supporting two topics of common European interest, namely– Software Defined Vehicle (SDV) and RISC V based design of ECS. These two topics, initially pursued independently, have naturally converged into joint actions targeting the development of industrially significant RISC V based platforms, which support the digital Vehicle-of-the-Future (VoF) paradigm. This talk will reveal the evolution and the current state-of-play of Chips JU’s activities in the fields of SDV and RISC V. The context will be the inevitable transformation of traditional automotive industry towards digitalization to meet the global challenges in the sector. Chips JU’s vision to employ RISC V based systems supporting SDV via hardware abstraction and consequently building a holistic digital platform for the VoF will be argued. This approach is seen as an advantageous strategic choice with significant potential impact, leading towards European technological sovereignty and more cost-efficient, thus more competitive and innovative, car manufacturing.
Bio: Dr. Georgi Kuzmanov obtained an engineering degree in Computer Systems from TU Sofia, Bulgaria and a PhD degree in Computer Engineering from TU Delft, the Netherlands, in 1998 and 2004 respectively. He started his professional career in industry as an IP and processor design engineer in 1997. Between 2000 and 2011, he was a researcher and a faculty member of the EEMCS faculty at TU Delft, where he is still lecturing. Since 2011, Georgi Kuzmanov has been serving as a programme officer for the ARTEMIS Joint Undertaking (JU), the ECSEL JU, the KDT JU, and recently the Chips JU. He has authored and co-authored nearly a hundred scientific publications, mainly in the fields of computer architecture and microarchitecture. His portfolio as a programme officer includes JU-funded projects on high-performance computing, RISC V, safety critical cyber-physical systems, software-defined vehicle, edge AI, neuromorphic chip design, and quantum computing, to name a few.
Automate Fault-Tolerant SoC Generation with the SOCRATES Platform
T2.7.03 (sub. #139), Wed 14 at 17:00, in Gaston Berger.
By Marco Andorno, CERN. Alessandro Caratelli, CERN. Benoît Denkinger, CERN. Kostas Kloukinas, CERN. Anvesh Nookala, CERN.
Abstract: SOCRATES is a SoC generator framework, specifically targeted at fault-tolerant architectures, developed for high-energy physics experiments, but extensible wherever high reliability is required. It allows to automatically build full SoCs starting from a collection of RISC-V CPU cores, IP blocks and interconnects. To do that, a custom build system, called SoCMake, takes care of managing dependencies and invoking the tools to generate both hardware and software components of the system. A silicon prototype has been designed and taped out to validate the toolkit and test the performance of the resulting architecture.
Panel – Accelerating Automotive Innovation with RISC-V: The journey from early adoption to industry wide deployment
T2.7.04, Wed 14 at 17:15, in Gaston Berger.
Moderated by Michael Chapman, Cortus.
Argument: The Automotive industry is already adopting RISC-V to deliver the vehicles of tomorrow, based on its open nature, ability to scale across all types of in-vehicle compute, and the support and supply options given by its global ecosystem of members. In this panel we will discuss how we can accelerate the momentum of RISC-V in automotive, the benefits of using an open standard, how we can ensure quality, safety and security required by automotive, the priorities we need to work on together and how we can build a software ecosystem together to deliver future automotive innovation.
Thursday 15, 09:00-10:30
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
Open Source Chip Design in the European Semiconductor Strategy
T3.1.01, Thu 15 at 09:00, in Gaston Berger.
By Stefan Wallentowitz, Professor, Hochschule München & FOSSi Foundation.
Abstract: Open source chip design has become part of the European strategy, particularly focusing on sovereignty, design access, productivity and talent. In this presentation, you will learn about open source chip design in Europe, how RISC-V plays an integral role in there and ongoing activities.
Bio: Stefan is a professor of Computer Engineering at Hochschule München University of Applied Sciences. He serves as vice-chair of the RISC-V board of directors and is director at FOSSi Foundation. He is a long term advocate of open standards and open source chip design.
Towards Open-Source and Automatic Performance Characterization Hardware
T3.1.03 (sub. #78), Thu 15 at 09:45, in Gaston Berger.
By Matthew E. Weingarten, Columbia University in the City of New York. Tanvir Ahmed Khan, University of Michigan.
Abstract: Performance characterization is the key to unlocking efficient utilization of the underlying processing system. Rapid developments in specialized computing and hardware/software co-design make performance characterization more challenging—as the underlying hardware changes, so must the performance monitoring hardware and the accompanying performance models. CPU vendors have successfully popularized the top-down micro-architectural analysis (TMA) methodology that is effective in identifying true bottlenecks in a processor while abstracting away the hardware implementation. Unfortunately, researchers and practitioners are often limited to open-source RISC-V processors that lack hardware support for TMA or any other systematic performance characterization methodology. Even the simple scalar in-order RocketCore has not implemented performance hardware capable of providing enough information to support TMA, let alone more complex Out-of-Order (OoO) and super scalar SonicBOOM core. Furthermore, the challenges of performance characterization are compounded by the ever-increasing heterogeneity and specialization of hardware, and a wholistic performance characterization methodology for an entire System-on-Chip (SoC) remains open-ended. Overall, the lack of hardware-supported performance characterization hamstrings the ability to evaluate new hardware designs, for performance tooling to adapt to modern hardware, or even programmers efficiently exploit the target hardware.
Efficient debug and trace of RISC-V systems: a hardware/software co-design approach
T3.1.04 (sub. #180), Thu 15 at 10:00, in Gaston Berger.
By Oana Alexandra Lazar, Tessent Embedded Analytics. Henrique Mendes, Tessent Embedded Analytics. Angelo Maldonado-Liu, Tessent Embedded Analytics.
Abstract: The development risks of novel RISC-V solutions are exacerbated by bugs which are increasingly complicated to root-cause in ever-larger and more complex systems. Current debugging solutions are intrusive, impacting program execution timing and potentially hiding Heisenbugs. Run-stop-step debuggers alone lack the depth of visibility needed to root-cause complex and timing-sensitive bugs. We propose a complete end-to-end solution for highly efficient tracing, minimally invasive logging, and accelerated run-stop-step debugging of any RISC-V system, with out-of-the-box support for custom instructions. We demonstrate that an approach using both hardware and software to their full extent increases the efficiency of RISC-V debug and trace.
Improvements to RISC-V Vector code generation in LLVM
T3.1.05 (sub. #199), Thu 15 at 10:15, in Gaston Berger.
By Luke Lau, Igalia. Alex Bradbury, Igalia.
Abstract: LLVM has had stable support for the RISC-V vector extension for the past several releases, with both forms of autovectorization – the loop vectorizer and the SLP (superword-level-parallelism) vectorizer – enabled by default, as well as a rich set of C intrinsics for the RVV programming model. A key focus since then has been on improving generated code performance. This submission explains the changes made in the middle-end and backend that have delivered these gains and looks ahead to future work.
Thursday 15, 10:30-11:30
Demos in Louis Armand East amphitheater (level -3).
Booths and posters in expo area's 3 levels.
Thursday 15, 11:30-13:00
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
RISC-V: Reaching New Orbits in Space Computing
T3.3.01, Thu 15 at 11:30, in Gaston Berger.
By Lucana Santos, Microelectronics Engineer, ESA.
Abstract: RISC-V in space is becoming a tangible reality, with several missions already flying it. This presentation highlights the European Space Agency (ESA) latest developments to advance the adoption of this open-source instruction set architecture (ISA) in space systems. The portfolio of RISC-V centred System-on-Chip (SoC) for space is growing, with new devices soon going to be manufactured and offered in the market. Such SoCs bring unique space-related features as well as technical and programmatical challenges, which are presented in this talk. RISC-V in space is further supported by ESA by promoting the design and implementation of high-performance, reliable IP cores, and the establishment of a robust software ecosystem. In addition, the Ultra Deep Submicron (UDSM) initiative will be presented, showing how advanced semiconductor technology development is further accelerating the integration of RISC-V into space-grade electronics. These advancements will enable future space missions and projects to fully leverage the benefits of an open, flexible, and scalable ISA, fostering innovation, reducing dependency on proprietary technologies, and enhancing long-term sustainability in the space industry.
Bio: Lucana Santos got her PhD in Telecommunications at the University of Las Palmas de Gran Canaria. She has several years of experience as researcher in the field of digital design for data processing on FPGAs and heterogeneous computing. She currently holds a position as Microelectronics Engineer for the European Space Agency, with a strong focus on digital IP and microprocessor design.
Unleashing the Power of RISC-V E-Trace with a Highly Efficient Software Decoder
T3.3.02 (sub. #128), Thu 15 at 11:45, in Gaston Berger.
By Marcel Zak, Siemens EDA. Mat O’Donnell, Siemens EDA. Vivek Chickermane, Siemens EDA.
Abstract: Debugging program misbehaviour that impacts large scale deployment of highly connected systems requires a robust debug infrastructure to monitor the instructions, data, and transactions between system components. The rapid adoption of RISC-V processors in mission critical applications has compelled system designers to rely on embedded trace monitors based on the RISC-V E-Trace specification to collect instruction trace data to analyse the trajectory of the transactions involving the CPU, memory, I/Os, peripherals, and other sub-systems. In this paper we describe a highly efficient software E-Trace Decoder that allows trace data to be non-intrusively captured at-speed. We describe two case studies to highlight the power of this implementation and provide quantitative data to show the efficiency of this implementation.
Challenge Accepted: Python Packaging Infrastructure for the RISCV64 Ecosystem
T3.3.03 (sub. #62), Thu 15 at 12:00, in Gaston Berger.
By Trevor Gamblin, BayLibre Inc. Mark D. Ryan, Rivos Inc. Julien Stephan, BayLibre Inc..
Abstract: As the RISC-V ecosystem grows with new platforms and higher performance, a key area of interest is its applicability towards scientific computing, data analysis, and machine learning. On other architectures such as ARM, these areas are already well-supported thanks to broad availability of binaries for critical packages such as NumPy, pandas, and PyTorch, but with RISC-V these are largely unavailable. The problem is further compounded by the challenge of building such packages manually, where even foundational examples such as NumPy take a prohibitively long time to build from source on commonly-available hardware, in addition to being prone to build errors and dependency chains that lead to long hours of sorting through confusing stack traces. The RISE project is tackling this problem by building, testing, deploying, and maintaining binaries for a selection of these packages. This creates a path forward for developers that wish to leverage current and upcoming RISC-V platforms for specialized research and industry applications
MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster
T3.3.04 (sub. #202), Thu 15 at 12:15, in Gaston Berger.
By Sergio Mazzola, Integrated Systems Laboratory, ETH Zürich. Yichao Zhang, Integrated Systems Laboratory, ETH Zürich. Marco Bertuletti, Integrated Systems Laboratory, ETH Zürich. Diyou Shen, Integrated Systems Laboratory, ETH Zürich. Luca Benini, Integrated Systems Laboratory, ETH Zürich.
Abstract: As computational paradigms evolve, applications such as attention-based models, wireless telecommunications, and computer vision impose increasingly challenging requirements on computer architectures: significant memory footprints and computing resources are demanded while maintaining flexibility and programmability at a low power budget. Thanks to their advantageous trade-offs, shared-L1-memory clusters have become a common building block of massively parallel computing architectures tackling these issues. MemPool is an open-source, RISC-V-based manycore cluster scaling up to 1024 processing elements (PEs). MemPool offers a scalable, extensible, and programmable solution to the challenges of shared-L1 clusters, establishing itself as an open-source research platform for architectural variants covering a wide trade-off space between versatility and performance. As a demonstration, this paper compares the three main MemPool flavors, Baseline MemPool, Systolic MemPool, and Vectorial MemPool, detailing their architecture, targets, and achieved trade-offs.
Compared Analysis of GCC Codegen for AArch64 and RISC-V
T3.3.05 (sub. #55), Thu 15 at 12:30, in Gaston Berger.
By Paul-Antoine Arras, BayLibre.
Abstract: This contribution explores possible improvements on GCC code generation for RISC-V. We collected dynamic instruction counts from selected SPEC CPU 2017 benchmarks and compared the results with AArch64. Findings reveal that prominent compiler weaknesses include missed unrolling opportunities, extra move instructions and suboptimal register allocation. Additionally, addressing ISA limitations, such as the lack of a scaled addressing mode, and vectorising library functions, like memset and math operations, are crucial for maximising RISC-V efficiency.
Thursday 15, 13:00-14:30
Demos in Louis Armand East amphitheater (level -3).
Booths and posters in expo area's 3 levels.
Thursday 15, 14:30-15:30
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
The Significance of the RVA23 Profile in Advancing RISC-V Ecosystem
T3.5.01, Thu 15 at 14:30, in Gaston Berger.
By Mark Hayter, Chief Strategy Officer & Co-Founder, RIVOS.
Abstract: The RVA23 profile represents a key development in the RISC-V architecture, standardizing the 64-bit application processors ISA for seamless software portability across hardware implementations. This simplifies development and supports RISC-V adoption in areas like servers, automotive and client devices, where binary compatibility is important. This presentation will look at the impact RVA23 and the platform specifications will have on high-performance applications processors and their adoption across a range of end use cases.
Bio: Mark Hayter is Chief Strategy Officer & Co-Founder of Rivos Inc. For the previous 11 years he was Senior Engineering Director in the Chrome OS Hardware team at Google. His team developed new technologies for Chromebooks, produced reference implementations and worked with OEMs to bring them to market. Prior to that he was involved in systems architecture at several semiconductor companies, being VP of Systems Engineering at P.A. Semi, Inc. (acquired by Apple Inc.), Senior Manager of Hardware Systems Engineering at Broadcom Corporation and System Architect at SiByte, Inc. Earlier, Hayter was at the Digital Equipment Corporation Systems Research Center. Hayter holds a PhD from the University of Cambridge Computer Laboratory.
Panel – Enterprise Linux Enablement on RISC-V
T3.5.04, Thu 15 at 14:45, in Gaston Berger.
Moderated by Isaac Chute, Director of Software Ecosystem, RISC-V International.
Argument: While building an open ISA is revolutionizing silicon development across Europe and the world at large, it needs to work hand in hand with the software ecosystem for it to be truly impactful in the marketplace. Europe is home to several centers of excellence within the Linux software distribution space. SUSE is based in the heart of Europe. Canonical too has it’s headquarters there. While Red Hat has its largest global engineering base in Brno, Česká republika. In essence a major portion of Open Source software development is driven from within the confines of Europe. Each of the major Enterprise Linux Distributions is investing in the enablement of the RISC-V platform, in essence collaborating in joint upstream development. Open Source is all about community where competitors collaborate to enable the future of tomorrow. Here is our chance to hear directly from the major Enterprise Distributions about their investment into this new and exciting future of the RISC-V software ecosystem which will drive technological innovation for decades to come.
Thursday 15, 16:30-17:30
Plenary keynotes and presentations in Gaston Berger anphitheater (level -2).
RISC-V open designs and contributions to hardware security research and development activities
T3.7.01, Thu 15 at 16:30, in Gaston Berger.
By Éric Saliba, Head of Scientific & Technical Division, ANSSI.
Abstract: This presentation provides a perspective on the technical challenges of securing components and the opportunities offered by open designs based on RISC-V, giving some recent examples of ANSSI contributions to open source projects or funded projects.
Bio: Éric Saliba is head of the Scientific and Technical Division of the French National Agency for Information Systems Security (ANSSI), which brings together laboratories that contribute to the definition and maintenance of the Agency’s technical guidelines and recommendations, and provides their expertise to its beneficiaries. Eric had worked for over twenty years on upstream studies and major research and development projects, both as an expert and technical manager.
OpenTitan Integrated: A RISC-V Open-Source Silicon Root-of-Trust for large SoCs
T3.7.02 (sub. #221), Thu 15 at 16:45, in Gaston Berger.
By Robert Schilling, Rivos Inc.. Samuel Ortiz, Rivos Inc.. Ravi Sahita, Rivos Inc.. Andreas Kurth, Lowrisc CIC.
Abstract: Modern System-on-Chips (SoCs) rely on a secure Root of Trust (RoT) as the foundation for all security services. Compromise of the RoT can have catastrophic consequences, undermining the security of the entire system.
This paper presents OpenTitan Integrated, an open-source silicon RoT based on RISC-V specifically tailored for integration into the complex security subsystems of large SoCs. OpenTitan Integrated extends the functionality of the discrete OpenTitan implementation by addressing the specific needs of integrated deployments. Key contributions include: 1) a clear interface trust boundary, defining secure communication paths and preventing privilege escalation; 2) a robust and standardized communication interface, enabling seamless interaction with other SoC components; and 3) a flexible register isolation mechanism, protecting sensitive registers in the system from unauthorized access and modification. These additions enable secure interaction with other SoC components and prevent unauthorized access, enhancing the overall security posture of the SoC.
Furthermore, OpenTitan Integrated’s open-source nature, available on GitHub under a permissive license, facilitates community review, independent verification, and enhances the overall security and trustworthiness of the design. This collaborative approach allows for rapid identification and mitigation of potential vulnerabilities, leading to a more robust and secure RoT.
Farewell and upcoming Summits
T3.7.03, Thu 15 at 17:00, in Gaston Berger.
By Teresa Cervero, RISC-V Summit Europe Steering Committee Chair, BSC.
Abstract: Some facts about the current, closing summit and some fresh news on the next ones.