Plenary sessions
Keynotes and presentations in the Gaston Berger amphitheatre (level -2)
Notes for plenary session presenters
Before the conference:
- Presenations shall be prepared as PPTX or PDF files.
- The final asbtract and slides are due for Monday, April 21st, 2025.
- At least one author of the poster must register for the core conference (Tuesday 13 to Thursday 15).
- The slides will be collected beforehand and displayed from a shared laptop.
Plenary sessions
Keynotes, invited talks, industrial and technical presentations in the Gaston Berger amphitheater.
Tuesday 13, 09:00-10:30
Welcome to the RISC-V Summit Europe 2025 in Paris
P1.1.1, Tue 13 at 09:00, in Gaston Berger.
By Christian Fabre, RISC-V Summit Europe 2025 Local Chair, CEA.
Program Overview of the RISC-V Summit Europe 2025
P1.1.2, Tue 13 at 09:05, in Gaston Berger.
By Borja Perez Paron, RISC-V Summit Europe 2025 Program Chair, Universidad de Cantabria.
RISC-V Technology Update
P1.1.3, Tue 13 at 09:15, in Gaston Berger.
By Andrea Gallo, RISC-V VP Technology, RISC-V.
The case for Open Source Hardware at Thales: Motivations and Recent Miletones with CVA6
P1.1.4, Tue 13 at 09:40, in Gaston Berger.
By Bernhard Quendt, Chief Technical Officer Thales Group, Thales.
Sovereignty, independence, innovation: 7 years of HW/SW codesign with RISC-V at CEA
P1.1.5, Tue 13 at 10:00, in Gaston Berger.
By Thomas Dombek, Head of Digital Integrated Circuits and Systems Department, CEA.
Enabling the Next Phase of RISC-V: Product Innovation and Scalable Solutions
P1.1.6, Tue 13 at 10:15, in Gaston Berger.
By Ning He, SVP and CTO, Eswin.
Tuesday 13, 11:30-13:00
RISC-V State of the Union
P1.2.1, Tue 13 at 11:30, in Gaston Berger.
By Krste Asanović, Chief Architect, SiFive.
RISC-V ISA Extensions with Hardware Acceleration for Hyperdimensional Computing
P1.2.2 (submission #109), Tue 13 at 12:00, in Gaston Berger.
By Rocco Martino, , Sapienza University of Rome.
Real-Time Extension to the RISC-V Advanced Interrupt Architecture
P1.2.3 (submission #206), Tue 13 at 12:15, in Gaston Berger.
By Alexey Khomich, , Synopsys Inc.
RISC-V Heterogeneous Computing Paradigm: Atomic IO Enqueue Extension and Virtualization
P1.2.4 (submission #148), Tue 13 at 12:30, in Gaston Berger.
By Ren Guo, , Alibaba Damo Academy.
Accelerating AI Models with Andes Matrix Multiplication (AMM) and RISC-V Vector (RVV) extensions: From CNNs to LLMs
P1.2.5 (submission #86), Tue 13 at 12:45, in Gaston Berger.
By I-WEI WU, , Andes Technology.
Tuesday 13, 14:30-15:30
The Custom Silicon Imperative: Addressing Manufacturing andSupply Chain Realities
P1.3.1, Tue 13 at 14:30, in Gaston Berger.
By Pablo Valerio, Supply Chain section Editor, EETimes.
RISC-V: Powering the Future of High Performance Computing?
P1.3.10, Tue 13 at 15:01, in Gaston Berger.
By Nick Brown, Senior Research Fellow, ECC.
Akeana, leveraging strong legacy to offer the broadest IP portfolio
P1.3.2, Tue 13 at 14:45, in Gaston Berger.
By Graham Wilson, Head of Product, Akeana.
Enter the RISC-V AI era with Andes
P1.3.3, Tue 13 at 14:47, in Gaston Berger.
By Niraj Dengale, Senior FAE, Andes Technology.
Getting towards first-time RISC-V silicon with automated end-to-end formal
P1.3.4, Tue 13 at 14:49, in Gaston Berger.
By Ashish Darbari, Founder & CEO, Axiomise.
Revolutionizing RISC-V Chip Design with AI Agents
P1.3.5, Tue 13 at 14:51, in Gaston Berger.
By David Wang, Founding Engineer, ChipAgents.ai.
(TBD)
P1.3.6, Tue 13 at 14:53, in Gaston Berger.
By Peter Shields, Senior Product Manager, Codasip.
Real-Time Trace: The Key to Streamlined Embedded System Development and Validation
P1.3.7, Tue 13 at 14:55, in Gaston Berger.
By Soufian Elmajdoub, Country Manager LAUTERBACH France, Lauterbach.
The LLVM Universe Project: What We Learned from openEuler RISC-V
P1.3.8, Tue 13 at 14:57, in Gaston Berger.
By Jingwei Wang, Engineer of the Institute of Software, Chinese Academy of Sciences, OpenEuler.
Semidynamics, NPU chip architecture reinvented for ultra-powerful AI with zero latency
P1.3.9, Tue 13 at 14:59, in Gaston Berger.
By Volker Politz, CSO, Semidynamics.
Tuesday 13, 16:30-18:00
Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE
P1.4.1 (submission #99), Tue 13 at 16:30, in Gaston Berger.
By Adeel Ahmad, , 10xEngineers.
Unlocking Performance, Profit, and Compliance: The RISC-V Approach to Medical AI
P1.4.2 (submission #170), Tue 13 at 16:45, in Gaston Berger.
By Raja Gopal Hari Vijay Sitharaman, , Zoho Corporation.
Flex-RV: World’s First Non-silicon RISC-V Microprocessor
P1.4.3 (submission #23), Tue 13 at 17:00, in Gaston Berger.
By Emre Ozer, , Pragmatic.
Wednesday 14, 09:00-10:30
A cloud first: Scaleway’s RISC-V servers
P2.1.1, Wed 14 at 09:00, in Gaston Berger.
By Fabien Piuzzi, Scaleway.
Enhancing your RISC-V SoC debug and optimization with embedded functional monitors
P2.1.2, Wed 14 at 09:30, in Gaston Berger.
By Mat O’Donnell, Software Architect Lead, Siemens.
XiangShan KMHv2: An Open Source RISC-V Core with >15/GHz for SPECCPU2006
P2.1.3, Wed 14 at 09:45, in Gaston Berger.
By Yungang Bao, Deputy director of ICT, CAS Chief Scientist of Beijing Institute of Open Source Chip , BOSC.
Beyond Innovation: RISC-V’s Path to Mass Adoption with Mature IP.
P2.1.4, Wed 14 at 10:00, in Gaston Berger.
By Wei-Han Lien, Chief Architect and Senior Fellow, Tenstorrent.
The case for Open Source Hardware at Thales: Motivations and Recent Miletones with CVA6
P2.1.5, Wed 14 at 10:15, in Gaston Berger.
By Bernhard Quendt, Chief Technical Officer Thales Group, Thales.
Wednesday 14, 11:30-13:00
A Safe Software Convergence: How Automotive and Industrial Designs are Eliminating Boundaries and Creating Opportunities
P2.2.1, Wed 14 at 11:30, in Gaston Berger.
By Edward Wilford, Senior Research Manager, Omdia.
Exhaustive Security Verification of CHERI Processors
P2.2.2 (submission #63), Wed 14 at 11:45, in Gaston Berger.
By Tobias Jauch, , RPTU Kaiserslautern-Landau.
The RISE Project: Advancing RISC-V Software
P2.2.3 (submission #171), Wed 14 at 12:00, in Gaston Berger.
By Jeffrey Osier-Mixon, , Red Hat.
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
P2.2.4 (submission #186), Wed 14 at 12:15, in Gaston Berger.
By Riccardo Tedeschi, , University of Bologna.
A RISC-V based accelerator for Post Quantum Cryptography
P2.2.5 (submission #112), Wed 14 at 12:30, in Gaston Berger.
By Ambily Suresh, , Silicon Austria Labs.
Implementing Runtime-Configurable Endianness in RISC-V: Challenges and Solutions
P2.2.6 (submission #105), Wed 14 at 12:45, in Gaston Berger.
By Lawrence Hunter, , Codethink.
Wednesday 14, 14:30-15:30
RISC-V: Powering the Future of High Performance Computing?
P2.3.1, Wed 14 at 14:30, in Gaston Berger.
By Nick Brown, Senior Research Fellow, ECC.
From Open Silicon to Sovereign Supercomputing: EuroHPC’s Vision for RISC-V
P2.3.2, Wed 14 at 14:45, in Gaston Berger.
By Alexandra Kourfali, Program Manager, EuroHPC.
Monte Cimone v2: Down the Road of RISC-V High-Performance Computers
P2.3.3 (submission #177), Wed 14 at 15:00, in Gaston Berger.
By Emanuele Venieri, , University of Bologna.
Ahead of Time Generation for GPSA Protection in RISC-V Embedded Cores
P2.3.4 (submission #124), Wed 14 at 15:15, in Gaston Berger.
By Louis Savary, , Inria.
Wednesday 14, 16:30-18:00
Chips JU and the Vehicle of the Future – a RISC V view
P2.4.1, Wed 14 at 16:30, in Gaston Berger.
By Georgi Kuzmanov, Programme Officer, Chips JU.
Automate Fault-Tolerant SoC Generation with the SOCRATES Platform
P2.4.3 (submission #139), Wed 14 at 17:00, in Gaston Berger.
By Marco Andorno, , CERN.
Thursday 15, 09:00-10:30
Open Source Chip Design in the European Semiconductor Strategy
P3.1.1, Thu 15 at 09:00, in Gaston Berger.
By Stefan Wallentowitz, Professor, Hochschule München & FOSSi Foundation.
Towards Open-Source and Automatic Performance Characterization Hardware
P3.1.3 (submission #78), Thu 15 at 09:45, in Gaston Berger.
By Matthew Weingarten, , Columbia University in the City of New York.
Efficient debug and trace of RISC-V systems: a hardware/software co-design approach
P3.1.4 (submission #180), Thu 15 at 10:00, in Gaston Berger.
By Oana Lazar, , Tessent Embedded Analytics.
Improvements to RISC-V Vector code generation in LLVM
P3.1.5 (submission #199), Thu 15 at 10:15, in Gaston Berger.
By Luke Lau, , Igalia.
Thursday 15, 11:30-13:00
RISC-V: Reaching New Orbits in Space Computing
P3.2.1, Thu 15 at 11:30, in Gaston Berger.
By Lucana Santos, Microelectronics Engineer, ESA.
Unleashing the Power of RISC-V E-Trace with a Highly Efficient Software Decoder
P3.2.2 (submission #128), Thu 15 at 11:45, in Gaston Berger.
By Marcel Zak, , Siemens EDA.
Challenge Accepted: Python Packaging Infrastructure for the RISCV64 Ecosystem
P3.2.3 (submission #62), Thu 15 at 12:00, in Gaston Berger.
By Trevor Gamblin, , BayLibre Inc.
MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster
P3.2.4 (submission #202), Thu 15 at 12:15, in Gaston Berger.
By Sergio Mazzola, , ETH Zürich.
Compared Analysis of GCC Codegen for AArch64 and RISC-V
P3.2.5 (submission #55), Thu 15 at 12:30, in Gaston Berger.
By Paul-Antoine Arras, , BayLibre.
Thursday 15, 14:30-15:30
The Significance of the RVA23 Profile in Advancing RISC-V Ecosystem
P3.3.1, Thu 15 at 14:30, in Gaston Berger.
By Mark Hayter, Chief Strategy Officer & Co-Founder, RIVOS.
Thursday 15, 16:30-17:30
RISC-V open designs and contributions to hardware security research and development activities
P3.4.1, Thu 15 at 16:30, in Gaston Berger.
By Éric Saliba, Head of Scientific & Technical Division, ANSSI.
OpenTitan Integrated: A RISC-V Open-Source Silicon Root-of-Trust for large SoCs
P3.4.2 (submission #221), Thu 15 at 16:45, in Gaston Berger.
By Robert Schilling, , Rivos Inc.
Farewell and upcoming Summits
P3.4.3, Thu 15 at 17:00, in Gaston Berger.
By Teresa Cervero, RISC-V Summit Europe Steering Committee Chair, BSC.