Presentations

The list of accepted presentations.

Notes for plenary session presenters

Before the conference:

Presenations shall be prepared as PPTX or PDF files.
The final asbtract and slides are due for Monday, April 21st, 2025.
At least one author of the poster must register for the core conference (Tuesday 13 to Thursday 15).
The slides will be collected beforehand and displayed from a shared laptop.

Industrial presentations

Accepted industrial presentations, sorted by last name of main contact.

Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE
Adeel Ahmad (10xEngineers)

Challenge Accepted: Python Packaging Infrastructure for the RISCV64 Ecosystem
Trevor Gamblin (BayLibre Inc)

Real-Time Extension to the RISC-V Advanced Interrupt Architecture
Alexey Khomich (Synopsys Inc)

Improvements to RISC-V Vector code generation in LLVM
Luke Lau (Igalia)

Efficient debug and trace of RISC-V systems: a hardware/software co-design approach
Oana Lazar (Tessent Embedded Analytics)

The RISE Project: Advancing RISC-V Software
Jeffrey Osier-Mixon (Red Hat)

A cloud first: Scaleway’s RISC-V servers
Fabien Piuzzi (Scaleway)

OpenTitan Integrated: A RISC-V Open-Source Silicon Root-of-Trust for large SoCs
Robert Schilling (Rivos Inc)

Unlocking Performance, Profit, and Compliance: The RISC-V Approach to Medical AI
Raja Gopal Hari Vijay Sitharaman (Zoho Corporation)

A RISC-V based accelerator for Post Quantum Cryptography
Ambily Suresh (Silicon Austria Labs)

Accelerating AI Models with Andes Matrix Multiplication (AMM) and RISC-V Vector (RVV) extensions: From CNNs to LLMs
I-WEI WU (Andes Technology)

Unleashing the Power of RISC-V E-Trace with a Highly Efficient Software Decoder
Marcel Zak (Siemens EDA)

Accepted technical presentations, sorted by last name of main contact.

Automate Fault-Tolerant SoC Generation with the SOCRATES Platform
Marco Andorno (CERN)

Compared Analysis of GCC Codegen for AArch64 and RISC-V
Paul-Antoine Arras (BayLibre)

RISC-V Heterogeneous Computing Paradigm: Atomic IO Enqueue Extension and Virtualization
Ren Guo (Alibaba Damo Academy)

Implementing Runtime-Configurable Endianness in RISC-V: Challenges and Solutions
Lawrence Hunter (Codethink)

Exhaustive Security Verification of CHERI Processors
Tobias Jauch (RPTU Kaiserslautern-Landau)

RISC-V ISA Extensions with Hardware Acceleration for Hyperdimensional Computing
Rocco Martino (Sapienza University of Rome)

MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster
Sergio Mazzola (ETH Zürich)

Flex-RV: World’s First Non-silicon RISC-V Microprocessor
Emre Ozer (Pragmatic)

Ahead of Time Generation for GPSA Protection in RISC-V Embedded Cores
Louis Savary (Inria)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
Riccardo Tedeschi (University of Bologna)

Monte Cimone v2: Down the Road of RISC-V High-Performance Computers
Emanuele Venieri (University of Bologna)

Towards Open-Source and Automatic Performance Characterization Hardware
Matthew Weingarten (Columbia University in the City of New York)